Toggle the RTC BUC control bit for Top Swap bootblock selection based on
the "attempt_slot_b" flag CMOS option, allowing to select which of the
BOOTBLOCK or TOP_SWAP regions to boot from.
This means that after an update, the CMOS option can be set to boot from
the newer TOP_SWAP bootblock. In case of failure, CMOS can be cleared to
revert to the known-good base BOOTBLOCK.
This is part of ongoing implementation of a redundancy feature proposed
on the mailing list:
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
Switching between identical bootblocks doesn't impact further boot flow,
i.e. selecting which FMAP region to load consecutive stages from.
That is to be enabled in following patches.
So far tested and enabled for the Alder Lake SoC.
TEST=Boot VP6650, setting the attempt_slot_b flag to different values,
observing that it resets/continues booting correctly.
Change-Id: Ib183a1f72ee8585b2c4ad4376344de33ff54cbb9
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
This commit implements support for the FSP_VGA_MODE12_MONOCHROME
Kconfig option within the Panther Lake romstage code.
By checking for the CONFIG_FSP_VGA_MODE12_MONOCHROME option, we
set the corresponding VGA_INIT_CONTROL_MODE12_MONOCHROME bit in
the FSP_M_CONFIG structure.
This ensures that when a 1-bit-per-pixel framebuffer is used, the
Intel FSP is correctly informed to replicate the data across the
remaining color planes for display, saving 75% of framebuffer memory
in romstage.
Key changes:
- Define the new VGA_INIT_CONTROL_MODE12_MONOCHROME control bit.
- Conditionally set this control bit in setup_vga_mode12_params()
when CONFIG_FSP_VGA_MODE12_MONOCHROME is enabled.
BUG=b:406725440
TEST=Verify VGA text rotation on Google/Felino.
Change-Id: I1dec24bb7ed44ca07babe0aa6886a50952d3faa2
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add common PCR write functions to write values directly to PCR
registers. These functions complement the existing read and
write-OR functions and provide a complete PCR access interface
for ACPI code.
WPCR: Generic PCR write function in the ACPI library
PCRW: PCH-specific PCR write function that calls WPCR
BUG=none
TEST=Build test on platforms using PCR functions. Verify ACPI code can
successfully write to PCR registers using the new functions.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I2c74dffda94a3ab34bd71177a3878b8d4c3119cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Add Kconfig INTEL_TOP_SWAP_SEPARATE_REGIONS. When enabled, place the
regular bootblock in BOOTBLOCK and the Top Swap bootblock in TOPSWAP
to simplify A B updates. This lays groundwork for redundancy where one
bootblock remains a read only golden copy and the other is replaceable.
No swap control logic is added in this change. The option depends on
INTEL_ADD_TOP_SWAP_BOOTBLOCK and defaults to n so existing builds are
unchanged. A custom .fmd is required with BOOTBLOCK and TOPSWAP added
at the end of the image.
Background and update flow are described here:
Link: https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5Y
V35/
TEST=Build and run Protectli VP6650 (ADL-P), boots successfully with
correct microcode
Change-Id: I489406dd8d08ad85bb46324d3d009acb49b6c52a
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Introduce the `USB3_PORT_TX_CFG` macro to simplify the definition of
`usb3_port_config` structures.
This macro allows platform code to easily configure the Transmit
De-emphasis (`tx_de_emp`) value for a specific USB 3.0 port (identified
by `ocpin`).
This improves readability and reduces boilerplate when tuning signal
integrity settings for different USB ports on the board.
TEST=Able to build and boot google/kinmen.
Change-Id: I42565e2c573dfcff244a81bf7bcb9749eca52c05
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add PCIe speed configuration for CPU root ports in FSP-M. Previously,
only PCH root port speed could be configured via FSP-S. Since CPU root
ports are initialized in FSP-M, they require configuration during
romstage.
This change uses the pcie_speed_control_to_upd() helper (now available
in the shared header) to convert devicetree PCIE_SPEED_control values
to FSP UPD indices. The configuration respects the pciexp_speed CMOS
option override if present, otherwise uses the devicetree setting.
TEST=Booted on mc_rpl1. Configured CPU RP to different PCIe speeds
(Gen1/Gen2/Gen3) via devicetree and verified correct link speed
negotiation with lspci for each configuration.
Change-Id: If3d871f238e7f063fef01c68cc371ae72ec9642c
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Include guards should cover the whole file.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Idbb7b26b31460ad5ac6b8a55a41eb274a8fcec92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
The console UART base address for Panther Lake is being updated from
0xfe036000 to 0xfe02c000 (as per FSP version 3272). This correction
ensures the console initializes with the correct UART base address.
TEST=Able to get FSP debug log while building google/fatcat.
Change-Id: Ic123189fb5689318a4940edcfcf206c32e3ccf26
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
This patch implements passing a "SerialIoUartDmaEnable" pointer to
FSP-S by parsing the devicetree.
Default (0) means PIO, while 1 means DMA.
Change-Id: Id0acfe0b30899a3019ea7e54067fc06cbc56bab6
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Extract PCIe RP clock configuration logic to a separate function,
following the same refactoring done for Meteor Lake in CB:89790.
Change-Id: I0abc48c066697199acfc7b77ee553e4e8c7b5119
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Extract the logic to configure PCIe RPs' clock source and clock request
signals to a separate function, so that the loop in `pcie_rp_init()` is
easier to reuse to program other PCIe-related settings.
While we're at it, make a few small improvements such as printing which
RP index is missing the clock structure definition as well as using the
`BIT()` macro (which is already used in `pcie_rp_init()`. Also retype a
few variables for the RP index, as it is never bigger than a `uint8_t`,
the type of the return value of the `get_max_pcie_port()` function.
Change-Id: I5583ef863630790cedd901e7bd30f4606f887a04
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
The USB port configuration macros (covering USB 2.0, 3.0, and TCSS) are
currently duplicated across multiple Intel SoC headers.
This patch refactors the definitions into a new, central IA common
header file. Moving these macros to a shared location eliminates
redundant code, simplifies maintenance, and ensures consistency across
platforms.
Specifically, this refactoring allows Intel Meteor Lake (MTL) and
Panther Lake (PTL) to immediately adopt the common definitions.
TEST=Able to build and boot google/kinmen.
Change-Id: I7fb1e4d100c6d72eba0e31f37aa58e6d741ceea6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89984
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Xeons implementation and the common intel implementation are identical
functionality wise so just use the common function.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I0ed42a93444e7cc0d339cf63cec4c4411b5b4f73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Retrieve SVID/SSID via devicetree and program to HDA device
BUG=b/458444964, b/454824561
TEST="lspci -s 00:1f.3 -x and check value in offset 0x2c-0x2f"
Change-Id: I6bf4b5f2cbce69429daabce83ab11c13272194f4
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89983
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
The code was indexing an array of clock sources using an RP index which
is not correct. As the intent of compliance mode seems to be to set all
clock sources to be free-running, do the same from a different place in
order to avoid potential out-of-bounds accesses.
To preserve original behaviour, exit early from `pcie_rp_init()`. While
this is rather crude, subsequent commits will refactor said function.
Change-Id: I89e6e9f85b7b86b0a74ece88641a378f2c0b599f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89788
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
`cfg[i].clk_req` is a `uint8_t` so use `%u` instead of `%d`.
Change-Id: I6c7a6ecbd2f5b917d44923d0ad6cb331d9bb054c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89789
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This commit implements the configuration of VGA mode 12 in the
Intel Pantherlake SoC's romstage. It integrates the newly added
text rendering API to display user messages using a planar buffer
instead of the standard VGA message string.
The changes include:
- A call to `render_text_to_bitmap_buffer()` to draw the message
on the bitmap buffer.
- Determining the display orientation from the common SoC
configuration, with an override for a closed lid.
- Calculating and setting the correct position of the rendered
text in the VGA buffer.
- Duplicating the single-plane bitmap data to all required planes
for VGA mode 12.
- Setting the `VGA_INIT_CONTROL_MODE12` bit in the FSP-M UPD
to inform FSP to use the new mode.
- Implementing the `soc_set_vga_mode12_buffer()` API to set the
corresponding FSP-M UPD for VGA mode12 buffer address.
BUG=b:406725440
TEST=Verify VGA text rotation on Google/Felino.
Change-Id: Ic69fff0479020a31c7e6f0c52b4bdb25b1483bb9
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Enable hardware-managed microphone privacy by setting the
PchHdaMicPrivacyMode FSP UPD to 1. This feature was enabled by
default in FSP previously but has since changed to disabled by
default, so now coreboot explicitly enables this as it is a desired
feature for Chrome platforms.
The hardware-managed microphone privacy feature allows the platform
to control the microphone mute state at the hardware level for
enhanced privacy.
TEST=Verify UPD value is set correctly and HW managed mic privacy is
working as expected.
Change-Id: I9a20bd129103aae35550104f6a7025484ef5e9c1
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88451
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <srinivas.kulkarni@intel.com>
This commit removes the explicit CONFIG_HAVE_BMP_LOGO_COMPRESS_LZMA
definition from the Panther Lake Kconfig.
This local Kconfig setting, previously defaulted to 'n', is redundant
because the Panther Lake build now correctly inherits the intended
system-wide default, which is to use LZMA compression for the BMP
splash screen.
Removing this unnecessary Kconfig option simplifies the configuration
and results in a measured ~3ms reduction in boot time during the
firmware splash screen rendering phase on Panther Lake platforms.
w/o this patch:
```
963:returning from FspMultiPhaseSiInit 1,096,797 (102,937)
17:starting LZ4 decompress (ignore for x86) 1,111,606 (14,808)
18:finished LZ4 decompress (ignore for x86) 1,111,641 (34)
17:starting LZ4 decompress (ignore for x86) 1,119,857 (8,216)
18:finished LZ4 decompress (ignore for x86) 1,119,879 (21)
```
w/ this patch
```
963:returning from FspMultiPhaseSiInit 1,097,817 (103,211)
15:starting LZMA decompress (ignore for x86) 1,110,058 (12,241)
16:finished LZMA decompress (ignore for x86) 1,111,096 (1,037)
15:starting LZMA decompress (ignore for x86) 1,117,554 (6,458)
16:finished LZMA decompress (ignore for x86) 1,117,906 (352)
```
Change-Id: I64579e53c7f307d1430767da04a413f80016487f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
The pcie_speed_control_to_upd() helper function was only available in
aspm.c for PCH root port configuration. However, CPU root ports in
romstage also need to convert PCIE_SPEED_control enum values to FSP
UPD indices.
Move pcie_speed_control_to_upd() from aspm.c to pcie_helpers.c to
make it available in both romstage and ramstage. This allows both
PCH and CPU root port code to use the same conversion logic without
code duplication.
The helper handles the mapping between devicetree enum values and FSP
UPD values using the UPD_INDEX() macro (which subtracts 1):
- SPEED_DEFAULT (0) -> SPEED_AUTO (1) -> UPD_INDEX = 0
- SPEED_AUTO (1) -> UPD_INDEX = 0
- SPEED_GEN1 (2) -> UPD_INDEX = 1
- SPEED_GEN2 (3) -> UPD_INDEX = 2
- SPEED_GEN3 (4) -> UPD_INDEX = 3
- SPEED_GEN4 (5) -> UPD_INDEX = 4
This accounts for the fact that FSP expects 0-based indexing where
0 = Auto, 1 = Gen1, 2 = Gen2, etc.
TEST=Configured PCIE_SPEED_GEN2 for root port on mc_rpl1, booted and
verified with lspci -vv that device is limited to Gen2 speed
Change-Id: I0f70ad4da6f9f9e73b1c05648f0b206d5d61e07d
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Update thermal design current (TDC) values for GT domain across
multiple PTL SKUs based on input from Power and Performance team.
BUG=none
TEST=Boot to OS on fatcat device and check performance.
Change-Id: I6333f8b5db8c7fc1739d0772d83bfe602a837a53
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89697
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Ma, Zhixing <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change the I2C connection speed type from uint32_t to the i2c_speed
enum type for better type safety and code consistency. While the
i2c_speed enum values correspond to actual speed values in Hz, using the
enum provides clearer intent and prevents invalid speed values.
Additionally, add logic to use standard I2C speed (100 kHz) when no
recommended or required speed is specified in the device tree, SoC
configuration, or device settings.
BUG=none
TEST=Boot Fatcat board to OS and verify correct I2C speed assignments in
'DSPD' Name object under THC device from SSDT. Confirm touch devices
operate at expected speeds.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ie01693544bebf9f748d16606fc13f39fe4069b03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89649
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
To modify the Top Swap Block Size in the FD (if provided and
CONFIG_HAVE_IFD_BIN=y), set the following Kconfig variables:
- CONFIG_INTEL_HAS_TOP_SWAP
- CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK
- CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE
- CONFIG_INTEL_IFD_SET_TOP_SWAP_BOOTBLOCK_SIZE
Needed for the bootblock redundancy feature suggested at
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
TEST=build VP66xx with custom Kconfig, check if TSBS is modified in FD
Change-Id: I94d3d3e2511a7e56392a9e34f845ae91602ce7f1
Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89493
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The touch controller's I2C bus speed configuration was previously set
directly through register values. This update introduces the use of the
I2C speed enum type to specify the desired connection speed, improving
clarity and reducing the risk of errors. A mapping function has been
added to convert the I2C speed enum into the appropriate register
value, factoring in the SoC's specific divider configuration. This
change ensures that the speed assignment aligns with the expected
operational parameters of the Panther Lake SoC touch controller.
BUG=none
TEST=Boot Fatcat board to OS and verify that the I2C speed assignments
are correct for the register value in SSDT.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I32e71ddcab77af2119c012bd3276f83c1bcea954
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
coreboot's resource allocator identifies and uses two MMIO windows
below 4GB, but currently only one is declared in the ACPI _CRS.
Normally this isn't a problem, as coreboot is usually able to allocate
resources entirely in the (declared) lower MMIO window. But, this is
problematic when using top-down allocation, since coreboot assigns
resources to devices starting in the (undeclared) upper MMIO window,
which the OS does not consider a valid space.
Linux will mostly handle this gracefully, and reassign BARs in the
lower MMIO address space. Windows does not, and will simply mark any
devices in the upper window as invalid or malfunctioning.
To resolve this, add the fixed-sized PM02 PCI MMIO window above MMCONF
to match the region used by coreboot's allocator.
With this change, both MMIO windows are properly reported via _CRS,
allowing the OS to use coreboot's resource allocations properly.
coreboot allocator:
[INFO ] * Base: 80000000, Size: 60000000, Tag: 200 [Window 1: 1.50GB]
[INFO ] * Base: f0000000, Size: e000000, Tag: 200 [Window 2: 224MB]
kernel before:
[mem 0x80000000-0xdfffffff window] [PM01: 1.50GB]
[mem 0xf4000000-0xfed44fff window] [TPM]
kernel after:
[mem 0x80000000-0xdfffffff window] [PM01: 1.50GB]
[mem 0xf0000000-0xfdffffff window] [PM02: 224MB]
[mem 0xfed40000-0xfed44fff window] [TPM]
BUG=https://ticket.coreboot.org/issues/611
TEST=Build/boot google/swanky with top-down allocation enabled.
Verify kernel sees both MMIO windows and devices keep their coreboot-
assigned BARs. Verify Windows boots with functional i2c devices.
Change-Id: Ibb61d3188f75a963e9417685c2808b27055b46d1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
coreboot's resource allocator identifies and uses two MMIO windows
below 4GB, but currently only one is declared in the ACPI _CRS.
Normally this isn't a problem, as coreboot is usually able to allocate
resources entirely in the (declared) lower MMIO window. But, this is
problematic when using top-down allocation, since coreboot assigns
resources to devices starting in the (undeclared) upper MMIO window,
which the OS does not consider a valid space.
Linux will mostly handle this gracefully, and reassign BARs in the
lower MMIO address space. Windows does not, and will simply mark any
devices in the upper window as invalid or malfunctioning.
To resolve this, add the fixed-sized PM02 PCI MMIO window above MMCONF
to match the region used by coreboot's allocator.
With this change, both MMIO windows are properly reported via _CRS,
allowing the OS to use coreboot's resource allocations properly.
coreboot allocator:
[INFO ] * Base: 80000000, Size: 60000000, Tag: 200 [Window 1: 1.50GB]
[INFO ] * Base: f0000000, Size: e000000, Tag: 200 [Window 2: 224MB]
kernel before:
[mem 0x80000000-0xdfffffff window] [PM01: 1.50GB]
[mem 0xf4000000-0xfed44fff window] [TPM]
kernel after:
[mem 0x80000000-0xdfffffff window] [PM01: 1.50GB]
[mem 0xf0000000-0xfdffffff window] [PM02: 224MB]
[mem 0xfed40000-0xfed44fff window] [TPM]
BUG=https://ticket.coreboot.org/issues/611
TEST=Build/boot google/edgar with top-down allocation enabled.
Verify kernel sees both MMIO windows and devices keep their coreboot-
assigned BARs. Verify Windows boots with functional i2c devices.
Change-Id: I86c38b6f0d3e31affb578dc7a1bf5c8109714bf5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89590
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates the power limit and voltage regulator parameters for
the Panther Lake SoC to align with the recommendations from the Power
Map 2.0 document (#813278). The update addresses discrepancies between
the previous configuration and the optimal settings specified in the
Power Map 2.0 document, ensuring better performance and efficiency.
TEST=Power and Performance team verified that Fatcat devices meet
requirements with these settings.
Change-Id: I2e11855c4f0533d826a25efead02ddcff9ab1f61
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Signed-off-by: Shaik Sameeruddin <shaik.sameeruddin@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89318
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
The wrong definition was used, so fix it.
Change-Id: I7ebbf0dcba4117ddeaa496b6faa83561d82c621d
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit introduces support for configuring power state current
thresholds (PS1, PS2, PS3) for each Voltage Regulator (VR) domain in the
Panther Lake SoC.
The thresholds allow platform integrators to specify current thresholds
(in 1/4 A increments, 0-128 A) for each VR domain and power state. A
value of 0 indicates AUTO (use default).
Change-Id: If4d473901c8de02b3d6cef44f5481a1864f14d63
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
This commit adds the capability to configure TDC mode and time window
for each Voltage Regulator (VR) domain, providing better control over
thermal constraints and power consumption.
The TDC mode specifies the method (iPL2 or Irms) used for thermal
management, while the time window determines the duration for current
averaging.
Change-Id: I2e11855c4f0533d826a25efead02ddcff9ab1f62
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Add configuration for Maximum Integrated Circuit Current (ICC) for
various SKUs and VR domains. The ICC values, defined in 1/4A increments,
specify the maximum allowable current for a given SKU and VR domain
configuration. This update enhances power management by allowing
tailored ICC settings.
Change-Id: I2c4712521da7b89cd4b2a6c499e11245b8eeb719
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88044
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit introduces configuration options for P-core and E-core
hysteresis time windows to support acoustic noise mitigation on Intel
Panther Lake (PTL) System on Chips (SoCs).
Change-Id: Ic3bceda06adf4e0a81b0503e5fb65895bfad2c12
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89333
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Only PmcLpmS0ixSubStateEnableMask is currently configured, and
PmcPchLpmS0ixSubStateEnableMask is left with the default value.
These should be the same.
Change-Id: I71bebec251c5c336407c2c173af29ddbfde0691b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This patch updates the Meteor Lake SoC configuration to select the
`FSP_DIMM_INFO` Kconfig option. This change instructs the build system
to use the common FSP driver implementation for retrieving and storing
DIMM information.
As a result, the duplicated, SoC-specific DIMM information retrieval
logic is dropped from the Panther Lake SoC code base, centralizing
the memory parsing mechanism.
TEST=Able to build and boot google/screebo. Verify the memory related
information is proper as part of the SMBIOS table.
Change-Id: I88fe72b558d2f9af55b585fd20f5f55e15eb465f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89496
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates the Panther Lake SoC configuration to select the
`FSP_DIMM_INFO` Kconfig option. This change instructs the build system
to use the common FSP driver implementation for retrieving and storing
DIMM information.
As a result, the duplicated, SoC-specific DIMM information retrieval
logic is dropped from the Panther Lake SoC code base, centralizing
the memory parsing mechanism.
TEST=Able to build and boot google/kinmen. Verify the memory
related information is proper as part of the SMBIOS table.
Change-Id: I3323d3add9213cc384b9a2ca978681287d0e1822
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit refactors the handling of CPU IDs for the Pantherlake and
Wildcat Lake series by using a single CPU ID mask instead of listing
each individual stepping. This change simplifies the code by reducing
redundancy and making it easier to manage CPU IDs.
Previously, each stepping of the Pantherlake series had its own entry,
which led to unnecessary complexity. By consolidating these into a
single entry with a mask, we improve maintainability and reduce
potential errors.
These modifications do not affect the existing functionality but
streamline the codebase for future updates and maintenance.
TEST=CPU ID c06c1 is properly identified as "Pantherlake".
Change-Id: Ie52ed860c096a3d157ae6580aeedf3acb8c723ab
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89375
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This moves most of the vendor and architecture independent code into
common ACPI code.
Change-Id: I7dca939612a5f3d8d6a148fa67bf0ce891952584
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88034
Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This rework is done gradually, and that means different mainboards will
use different implementations of the verb table. As this code is used by
multiple mainboards we need to keep both implementations and select
whichever implementation matches the one being used by the mainboard
currently being built.
It should be noted that we do not modifiy the verb tables in any case,
as it would break the regression test script mentioned in the TEST
section below.
For an overall rationale for this rework, see CB:88656.
TEST=
1. Timeless build with AZALIA_USE_LEGACY_VERB_TABLE=y produces
identical binaries (tested with google/auron_paine)
2. Passed regression test (CB:88763)
Change-Id: I9ba3259defae66678c4490891b869b96b6c6ade3
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88738
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Renames fill_fsps_acoustic_params to fill_fspm_acoustic_params to align
with the naming conventions used for other FSP-M configuration
functions.
Change-Id: I0044c21a8f82dfa2308fade78adbd8bcf844cb63
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit introduces a debug message to the DDR5 memory type
initialization process within the Panther Lake SoC. By adding this log,
developers can gain better insights when diagnosing issues related to
DDR5 memory configurations.
BUG=none
TEST=Verify the debug message is displayed during DDR5 initialization.
Change-Id: I77ceea0f7a29983dd2e4ad1af26a0383721d7ca0
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89331
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit removes the unused `lp_ddr_dq_dqs_re_training` field from
various memory configuration structures across multiple mainboard
variants, including google/fatcat, google/ocelot, and intel/ptlrvp.
This change should reduce complexity and prevent unnecessary memory
operations related to DQ/DQS retraining.
Write DqDqs retraining is enabled in Intel FSP by default. This can be
verified with debug FSP logs by checking WRTRETRAIN and
"MRC task -- Write DQ/DQS Retraining -- Started." prints.
BUG=None
TEST=Boot to OS on google fatcat board and verify DQ/DQS retraining.
Change-Id: Ib298b06260f576bee1f078dc09b1e23a9772b431
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89334
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit f3211e9639 ("soc/intel/pantherlake: Add support for Acoustic
Noise Mitigation UPDs") introduced minor coding convention
violations. These are being addressed as follows:
- Renames fill_fsps_acoustic_params to fill_fspm_acoustic_params to
align with the naming conventions used for other FSP-M configuration
functions.
- Removes an unnecessary empty line.
- Aligns function parameters.
Change-Id: I8652c2fee71c8e2742146b5e622633de78c1c17e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89332
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
In order to build for PantherLake with TME disabled, key generation
needs to depend on TME Kconfig.
Change-Id: I0af438e279f422292302387442489bcbc1b1605f
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89226
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit addresses a potential low power state over-consumption
issue. This issue could arise if SPI DMA has been locked down while a
transfer was still marked as active, typically if a SPI DMA transfer
failed and hung.
The fast_spi_dma_lock() function now checks if a DMA transfer is ongoing
and ensures that it is marked as complete before locking the DMA control
register.
Change-Id: I5e08991b2160a43013b129d302c46fc229f2286d
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88913
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
This commit adds support for a new Panther Lake B0 SKU CPUID c06c3.
BUG=b:444497427
TEST=Successfully boot a fatcat device with new Panther Lake B0.
coreboot displays the following log:
CPU: ID c06c3, Pantherlake B0, ucode: 0000010c
Change-Id: Id2c1caf8d6845bb16a94314c4e9a214def06efee
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89150
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
SlowSlewRate, AcousticNoiseMitigation and FastPkgCRampDisable upds
can be overwritten with this patch.
BUG=none
TEST=Able to override the acoustic noise UPDs.
Change-Id: I5bfa98834f8d7cfcaab3fdbb7dde914d78529581
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add mapping of different SKUs based on CPU ID and TDP values.
Add PowerLimits (PL) values.
Add i_trip value for Fast Vmode.
Note: The i_trip value, the value at which the Voltage Regulator (VR)
or SoC will trigger a protective action such as throttling or
entering Fast Vmode is, due to not being documented, currently set at
70% of the maximum current the VR is designed to support for a rail.
The actual i_trip value to be updated once it is available.
Ref=858124 Power Delivery Guide Rev1p0
830097 Powermap Rev1p1
BUG=b:433211504
TEST= Build Ocelot and verify it compiles without any error.
check CPU log for the following error
[ERROR] Could not find the SKU power map
With the current patch this error line is not seen in the CPU log
anymore.
Change-Id: I8c54efc8eb360ed6f814a336448bb204d5ab0268
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88858
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit introduces a new configuration structure for the
Connectivity Integration (CNVi) block in Intel SoCs.
The added soc_intel_common_block_cnvi_config structure, located in
chip.h, defines a wake pin that specifies the ACPI Power Resources for
Wake (_PRW), enabling wake-up capabilities from sleep states.
This enhancement provides a structured way to handle CNVi
configurations, which is crucial for managing device power states and
ensuring proper wake functionalities as defined by ACPI standards.
Change-Id: Ide6dea04cb089d73fe6aad9fb91044f9eb43edc6
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
