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soc/intel/pantherlake: Standardize macros for core count and SKUs

Browse source 
This patch updates macro names and enum values to follow consistent
naming conventions and improve code maintainability. Core count macros
and SKUs are renamed for clarity:
	PTL_U_1_CORE -> PTL_CORE_1
	PTL_U_2_CORE -> PTL_CORE_2
	PTL_H_1_CORE -> PTL_CORE_3
	PTL_H_2_CORE -> PTL_CORE_4
The soc_intel_pantherlake_sku enumeration is updated to use
standardized naming patterns. All references have been updated
accordingly.

Change-Id: Ibd8935715ff78571c0cce8617851da86ea11ded2
Signed-off-by: Sowmya <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89266
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sowmya 2025-09-18 19:07:31 +05:30 • committed by Jérémy Compostella
commit 6185983028
9 changed files with 62 additions and 66 deletions
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6
src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb
View file

@ -85,17 +85,17 @@ chip soc/intel/pantherlake
register "cep_enable[VR_DOMAIN_GT]" = "true"
register "enable_fast_vmode[VR_DOMAIN_SA]" = "true"
register "cep_enable[VR_DOMAIN_SA]" = "true"
register "fast_vmode_i_trip[PTL_U_1_CORE]" = "{
register "fast_vmode_i_trip[PTL_CORE_1]" = "{
[VR_DOMAIN_IA] = 63 * 4,
[VR_DOMAIN_GT] = 38 * 4,
[VR_DOMAIN_SA] = 38 * 4
}"
register "fast_vmode_i_trip[PTL_U_2_CORE]" = "{
register "fast_vmode_i_trip[PTL_CORE_2]" = "{
[VR_DOMAIN_IA] = 63 * 4,
[VR_DOMAIN_GT] = 38 * 4,
[VR_DOMAIN_SA] = 38 * 4
}"
register "fast_vmode_i_trip[PTL_H_1_CORE]" = "{
register "fast_vmode_i_trip[PTL_CORE_3]" = "{
[VR_DOMAIN_IA] = 75 * 4,
[VR_DOMAIN_GT] = 75 * 4,
[VR_DOMAIN_SA] = 38 * 4

22
src/mainboard/google/fatcat/variants/baseboard/fatcat/ramstage.c
View file

@ -25,67 +25,67 @@ const struct cpu_tdp_power_limits power_optimized_limits[] = {
{
.mch_id = PCI_DID_INTEL_PTL_H_ID_1,
.cpu_tdp = TDP_25W,
.power_limits_index = PTL_H_1_CORE,
.power_limits_index = PTL_CORE_3,
COMMON_PTL_H_POWER_LIMITS
},
{
.mch_id = PCI_DID_INTEL_PTL_H_ID_2,
.cpu_tdp = TDP_25W,
.power_limits_index = PTL_H_1_CORE,
.power_limits_index = PTL_CORE_3,
COMMON_PTL_H_POWER_LIMITS
},
{
.mch_id = PCI_DID_INTEL_PTL_H_ID_3,
.cpu_tdp = TDP_25W,
.power_limits_index = PTL_H_2_CORE,
.power_limits_index = PTL_CORE_4,
COMMON_PTL_H_POWER_LIMITS
},
{
.mch_id = PCI_DID_INTEL_PTL_H_ID_4,
.cpu_tdp = TDP_25W,
.power_limits_index = PTL_H_2_CORE,
.power_limits_index = PTL_CORE_4,
COMMON_PTL_H_POWER_LIMITS
},
{
.mch_id = PCI_DID_INTEL_PTL_H_ID_5,
.cpu_tdp = TDP_25W,
.power_limits_index = PTL_H_2_CORE,
.power_limits_index = PTL_CORE_4,
COMMON_PTL_H_POWER_LIMITS
},
{
.mch_id = PCI_DID_INTEL_PTL_H_ID_6,
.cpu_tdp = TDP_25W,
.power_limits_index = PTL_H_2_CORE,
.power_limits_index = PTL_CORE_4,
COMMON_PTL_H_POWER_LIMITS
},
{
.mch_id = PCI_DID_INTEL_PTL_H_ID_7,
.cpu_tdp = TDP_25W,
.power_limits_index = PTL_H_2_CORE,
.power_limits_index = PTL_CORE_4,
COMMON_PTL_H_POWER_LIMITS
},
{
.mch_id = PCI_DID_INTEL_PTL_H_ID_8,
.cpu_tdp = TDP_25W,
.power_limits_index = PTL_H_2_CORE,
.power_limits_index = PTL_CORE_4,
COMMON_PTL_H_POWER_LIMITS
},
{
.mch_id = PCI_DID_INTEL_PTL_U_ID_1,
.cpu_tdp = TDP_15W,
.power_limits_index = PTL_U_1_CORE,
.power_limits_index = PTL_CORE_1,
COMMON_PTL_U_POWER_LIMITS
},
{
.mch_id = PCI_DID_INTEL_PTL_U_ID_2,
.cpu_tdp = TDP_15W,
.power_limits_index = PTL_U_2_CORE,
.power_limits_index = PTL_CORE_2,
COMMON_PTL_U_POWER_LIMITS
},
{
.mch_id = PCI_DID_INTEL_PTL_U_ID_3,
.cpu_tdp = TDP_15W,
.power_limits_index = PTL_U_2_CORE,
.power_limits_index = PTL_CORE_2,
COMMON_PTL_U_POWER_LIMITS
},
};

6
src/mainboard/google/fatcat/variants/felino/overridetree.cb
View file

@ -43,17 +43,17 @@ end
chip soc/intel/pantherlake
register "power_limits_config[PTL_U_1_CORE]" = "{
register "power_limits_config[PTL_CORE_1]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 25,
}"
register "power_limits_config[PTL_H_1_CORE]" = "{
register "power_limits_config[PTL_CORE_3]" = "{
.tdp_pl1_override = 25,
.tdp_pl2_override = 25,
}"
register "power_limits_config[PTL_H_2_CORE]" = "{
register "power_limits_config[PTL_CORE_4]" = "{
.tdp_pl1_override = 25,
.tdp_pl2_override = 25,
}"

4
src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
View file

@ -23,13 +23,13 @@ chip soc/intel/pantherlake
# The initial version temporarily uses the PTL-H,
# but the thermal design is based on the PTL-U.
# Apply PTL-U's thermal settings here to avoid thermal issues.
register "power_limits_config[PTL_H_1_CORE]" = "{
register "power_limits_config[PTL_CORE_3]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 55,
.tdp_pl4 = 152,
}"
register "power_limits_config[PTL_H_2_CORE]" = "{
register "power_limits_config[PTL_CORE_4]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 55,
.tdp_pl4 = 152,

6
src/mainboard/google/fatcat/variants/lapis/overridetree.cb
View file

@ -1,16 +1,16 @@
chip soc/intel/pantherlake
register "power_limits_config[PTL_U_1_CORE]" = "{
register "power_limits_config[PTL_CORE_1]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 25,
}"
register "power_limits_config[PTL_H_1_CORE]" = "{
register "power_limits_config[PTL_CORE_3]" = "{
.tdp_pl1_override = 25,
.tdp_pl2_override = 25,
}"
register "power_limits_config[PTL_H_2_CORE]" = "{
register "power_limits_config[PTL_CORE_4]" = "{
.tdp_pl1_override = 25,
.tdp_pl2_override = 25,
}"

4
src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
View file

@ -23,13 +23,13 @@ chip soc/intel/pantherlake
# The initial version temporarily uses the PTL-H,
# but the thermal design is based on the PTL-U.
# Apply PTL-U's thermal settings here to avoid thermal issues.
register "power_limits_config[PTL_H_1_CORE]" = "{
register "power_limits_config[PTL_CORE_3]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 55,
.tdp_pl4 = 152,
}"
register "power_limits_config[PTL_H_2_CORE]" = "{
register "power_limits_config[PTL_CORE_4]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 55,
.tdp_pl4 = 152,

12
src/soc/intel/pantherlake/bootblock/report_platform.c
View file

@ -54,9 +54,9 @@ static struct {
const char *name;
} pch_table[] = {
{ PCI_DID_INTEL_PTL_U_H_ESPI_0, "Pantherlake SOC-UH" },
{ PCI_DID_INTEL_PTL_U_H_ESPI_1, "Pantherlake SOC-UH SuperSKU" },
{ PCI_DID_INTEL_PTL_U_H_ESPI_2, "Pantherlake SOC-UH Premium" },
{ PCI_DID_INTEL_PTL_U_H_ESPI_3, "Pantherlake SOC-UH Base" },
{ PCI_DID_INTEL_PTL_U_H_ESPI_1, "Pantherlake SOC-UH" },
{ PCI_DID_INTEL_PTL_U_H_ESPI_2, "Pantherlake SOC-UH" },
{ PCI_DID_INTEL_PTL_U_H_ESPI_3, "Pantherlake SOC-UH" },
{ PCI_DID_INTEL_PTL_U_H_ESPI_4, "Pantherlake SOC-UH" },
{ PCI_DID_INTEL_PTL_U_H_ESPI_5, "Pantherlake SOC-UH" },
{ PCI_DID_INTEL_PTL_U_H_ESPI_6, "Pantherlake SOC-UH" },
@ -86,9 +86,9 @@ static struct {
{ PCI_DID_INTEL_PTL_U_H_ESPI_30, "Pantherlake SOC-UH" },
{ PCI_DID_INTEL_PTL_U_H_ESPI_31, "Pantherlake SOC-UH" },
{ PCI_DID_INTEL_PTL_H_ESPI_0, "Pantherlake SOC-H" },
{ PCI_DID_INTEL_PTL_H_ESPI_1, "Pantherlake SOC-H SuperSKU" },
{ PCI_DID_INTEL_PTL_H_ESPI_2, "Pantherlake SOC-H Premium" },
{ PCI_DID_INTEL_PTL_H_ESPI_3, "Pantherlake SOC-H Base" },
{ PCI_DID_INTEL_PTL_H_ESPI_1, "Pantherlake SOC-H" },
{ PCI_DID_INTEL_PTL_H_ESPI_2, "Pantherlake SOC-H" },
{ PCI_DID_INTEL_PTL_H_ESPI_3, "Pantherlake SOC-H" },
{ PCI_DID_INTEL_PTL_H_ESPI_4, "Pantherlake SOC-H" },
{ PCI_DID_INTEL_PTL_H_ESPI_5, "Pantherlake SOC-H" },
{ PCI_DID_INTEL_PTL_H_ESPI_6, "Pantherlake SOC-H" },

48
src/soc/intel/pantherlake/chip.h
View file

@ -53,11 +53,11 @@ enum soc_intel_pantherlake_sagv_gears {
};
enum soc_intel_pantherlake_power_limits {
PTL_U_1_CORE,
PTL_U_2_CORE,
PTL_H_1_CORE,
PTL_H_2_CORE,
PTL_H_3_CORE,
PTL_CORE_1,
PTL_CORE_2,
PTL_CORE_3,
PTL_CORE_4,
PTL_CORE_5,
WCL_CORE,
PTL_POWER_LIMITS_COUNT,
};
@ -70,11 +70,11 @@ enum soc_intel_pantherlake_cpu_tdps {
};
enum soc_intel_pantherlake_sku {
PTL_H404_SKU,
PTL_H12XE_SKU,
PTL_H484_SKU,
PTL_H4XE_SKU,
PTL_H204_SKU,
PTL_SKU_1,
PTL_SKU_2,
PTL_SKU_3,
PTL_SKU_4,
PTL_SKU_5,
WCL_SKU_1,
WCL_SKU_2,
WCL_SKU_3,
@ -90,20 +90,20 @@ static const struct soc_intel_pantherlake_power_map {
enum soc_intel_pantherlake_cpu_tdps cpu_tdp;
enum soc_intel_pantherlake_sku sku;
} cpuid_to_ptl[] = {
{ PCI_DID_INTEL_PTL_U_ID_1, PTL_U_1_CORE, TDP_15W, PTL_H404_SKU },
{ PCI_DID_INTEL_PTL_U_ID_1, PTL_U_1_CORE, TDP_25W, PTL_H404_SKU },
{ PCI_DID_INTEL_PTL_U_ID_2, PTL_U_2_CORE, TDP_15W, PTL_H204_SKU },
{ PCI_DID_INTEL_PTL_U_ID_2, PTL_U_2_CORE, TDP_25W, PTL_H204_SKU },
{ PCI_DID_INTEL_PTL_U_ID_3, PTL_U_2_CORE, TDP_15W, PTL_H404_SKU },
{ PCI_DID_INTEL_PTL_U_ID_3, PTL_U_2_CORE, TDP_25W, PTL_H404_SKU },
{ PCI_DID_INTEL_PTL_H_ID_1, PTL_H_1_CORE, TDP_25W, PTL_H12XE_SKU },
{ PCI_DID_INTEL_PTL_H_ID_2, PTL_H_1_CORE, TDP_25W, PTL_H484_SKU },
{ PCI_DID_INTEL_PTL_H_ID_3, PTL_H_2_CORE, TDP_25W, PTL_H12XE_SKU },
{ PCI_DID_INTEL_PTL_H_ID_4, PTL_H_2_CORE, TDP_25W, PTL_H12XE_SKU },
{ PCI_DID_INTEL_PTL_H_ID_5, PTL_H_2_CORE, TDP_25W, PTL_H4XE_SKU },
{ PCI_DID_INTEL_PTL_H_ID_6, PTL_H_2_CORE, TDP_25W, PTL_H4XE_SKU },
{ PCI_DID_INTEL_PTL_H_ID_7, PTL_H_2_CORE, TDP_25W, PTL_H4XE_SKU },
{ PCI_DID_INTEL_PTL_H_ID_8, PTL_H_2_CORE, TDP_25W, PTL_H12XE_SKU },
{ PCI_DID_INTEL_PTL_U_ID_1, PTL_CORE_1, TDP_15W, PTL_SKU_1 },
{ PCI_DID_INTEL_PTL_U_ID_1, PTL_CORE_1, TDP_25W, PTL_SKU_1 },
{ PCI_DID_INTEL_PTL_U_ID_2, PTL_CORE_2, TDP_15W, PTL_SKU_5 },
{ PCI_DID_INTEL_PTL_U_ID_2, PTL_CORE_2, TDP_25W, PTL_SKU_5 },
{ PCI_DID_INTEL_PTL_U_ID_3, PTL_CORE_2, TDP_15W, PTL_SKU_1 },
{ PCI_DID_INTEL_PTL_U_ID_3, PTL_CORE_2, TDP_25W, PTL_SKU_1 },
{ PCI_DID_INTEL_PTL_H_ID_1, PTL_CORE_3, TDP_25W, PTL_SKU_2 },
{ PCI_DID_INTEL_PTL_H_ID_2, PTL_CORE_3, TDP_25W, PTL_SKU_3 },
{ PCI_DID_INTEL_PTL_H_ID_3, PTL_CORE_4, TDP_25W, PTL_SKU_2 },
{ PCI_DID_INTEL_PTL_H_ID_4, PTL_CORE_4, TDP_25W, PTL_SKU_2 },
{ PCI_DID_INTEL_PTL_H_ID_5, PTL_CORE_4, TDP_25W, PTL_SKU_4 },
{ PCI_DID_INTEL_PTL_H_ID_6, PTL_CORE_4, TDP_25W, PTL_SKU_4 },
{ PCI_DID_INTEL_PTL_H_ID_7, PTL_CORE_4, TDP_25W, PTL_SKU_4 },
{ PCI_DID_INTEL_PTL_H_ID_8, PTL_CORE_4, TDP_25W, PTL_SKU_2 },
{ PCI_DID_INTEL_WCL_ID_1, WCL_CORE, TDP_15W, WCL_SKU_1},
{ PCI_DID_INTEL_WCL_ID_2, WCL_CORE, TDP_15W, WCL_SKU_2},
{ PCI_DID_INTEL_WCL_ID_3, WCL_CORE, TDP_15W, WCL_SKU_3},

20
src/soc/intel/pantherlake/chipset_ptl.cb
View file

@ -2,48 +2,44 @@ chip soc/intel/pantherlake
device cpu_cluster 0 on end
# H404
register "power_limits_config[PTL_U_1_CORE]" = "{
register "power_limits_config[PTL_CORE_1]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 55,
.tdp_pl4 = 163,
.tdp_pl4_fastvmode = 150,
}"
register "thermal_design_current[PTL_H404_SKU]" = "{
register "thermal_design_current[PTL_SKU_1]" = "{
[VR_DOMAIN_IA] = 34 * 8,
[VR_DOMAIN_GT] = 23 * 8
}"
# H204
register "power_limits_config[PTL_U_2_CORE]" = "{
register "power_limits_config[PTL_CORE_2]" = "{
.tdp_pl1_override = 15,
.tdp_pl2_override = 45,
.tdp_pl4 = 105,
.tdp_pl4_fastvmode = 95,
}"
register "thermal_design_current[PTL_H204_SKU]" = "{
register "thermal_design_current[PTL_SKU_5]" = "{
[VR_DOMAIN_IA] = 23 * 8,
[VR_DOMAIN_GT] = 23 * 8
}"
# H12Xe and H484
register "power_limits_config[PTL_H_1_CORE]" = "{
register "power_limits_config[PTL_CORE_3]" = "{
.tdp_pl1_override = 25,
.tdp_pl2_override = 64,
.tdp_pl4 = 175,
.tdp_pl4_fastvmode = 160,
}"
register "thermal_design_current[PTL_H12XE_SKU]" = "{
register "thermal_design_current[PTL_SKU_2]" = "{
[VR_DOMAIN_IA] = 39 * 8,
[VR_DOMAIN_GT] = 44 * 8
}"
register "thermal_design_current[PTL_H484_SKU]" = "{
register "thermal_design_current[PTL_SKU_3]" = "{
[VR_DOMAIN_IA] = 39 * 8,
[VR_DOMAIN_GT] = 23 * 8
}"
# H4XE
register "power_limits_config[PTL_H_2_CORE]" = "{
register "power_limits_config[PTL_CORE_4]" = "{
.tdp_pl1_override = 25,
.tdp_pl2_override = 64,
.tdp_pl4 = 154,