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soc/intel/baytrail/acpi: Add missing MMIO window below 4GB

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coreboot's resource allocator identifies and uses two MMIO windows
below 4GB, but currently only one is declared in the ACPI _CRS.
Normally this isn't a problem, as coreboot is usually able to allocate
resources entirely in the (declared) lower MMIO window. But, this is
problematic when using top-down allocation, since coreboot assigns
resources to devices starting in the (undeclared) upper MMIO window,
which the OS does not consider a valid space.

Linux will mostly handle this gracefully, and reassign BARs in the
lower MMIO address space. Windows does not, and will simply mark any
devices in the upper window as invalid or malfunctioning.

To resolve this, add the fixed-sized PM02 PCI MMIO window above MMCONF
to match the region used by coreboot's allocator.

With this change, both MMIO windows are properly reported via _CRS,
allowing the OS to use coreboot's resource allocations properly.

coreboot allocator:
[INFO ]   * Base: 80000000, Size: 60000000, Tag: 200  [Window 1: 1.50GB]
[INFO ]   * Base: f0000000, Size:  e000000, Tag: 200  [Window 2:  224MB]

kernel before:
[mem 0x80000000-0xdfffffff window]  [PM01: 1.50GB]
[mem 0xf4000000-0xfed44fff window]  [TPM]

kernel after:
[mem 0x80000000-0xdfffffff window]  [PM01: 1.50GB]
[mem 0xf0000000-0xfdffffff window]  [PM02:  224MB]
[mem 0xfed40000-0xfed44fff window]  [TPM]

BUG=https://ticket.coreboot.org/issues/611

TEST=Build/boot google/swanky with top-down allocation enabled.
Verify kernel sees both MMIO windows and devices keep their coreboot-
assigned BARs. Verify Windows boots with functional i2c devices.

Change-Id: Ibb61d3188f75a963e9417685c2808b27055b46d1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Walter Sonius <walterav1984@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Matt DeVillier 2025-10-14 16:30:12 -05:00
commit 6b93516e02
1 changed files with 8 additions and 2 deletions
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10
src/soc/intel/baytrail/acpi/southcluster.asl
View file

@ -135,11 +135,17 @@ Name (MCRS, ResourceTemplate()
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000,,, LMEM)
/* PCI Memory Region (Top of memory-CONFIG_ECAM_MMCONF_BASE_ADDRESS) */
/* PCI Memory Region (TOLM - CONFIG_ECAM_MMCONF_BASE_ADDRESS) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000,,, PMEM)
0x00000000,,, PMEM)
/* PCI Memory Region above MMCONF (0xf0000000 - 0xfdffffff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0xf0000000, 0xfdffffff, 0x00000000,
0x0e000000,,, PM02)
/* TPM Area (0xfed40000-0xfed44fff) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,