soc/intel/ptl: Add Wildcat Lake SKU power map

Add mapping of different SKUs based on CPU ID and TDP values.
Add PowerLimits (PL) values.
Add i_trip value for Fast Vmode.

Note: The i_trip value, the value at which the Voltage Regulator (VR)
or SoC will trigger a protective action such as throttling or
entering Fast Vmode is, due to not being documented, currently set at
70% of the maximum current the VR is designed to support for a rail.
The actual i_trip value to be updated once it is available.

Ref=858124 Power Delivery Guide Rev1p0
    830097 Powermap Rev1p1

BUG=b:433211504
TEST= Build Ocelot and verify it compiles without any error.
check CPU log for the following error

    [ERROR]  Could not find the SKU power map

With the current patch this error line is not seen in the CPU log
anymore.

Change-Id: I8c54efc8eb360ed6f814a336448bb204d5ab0268
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88858
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>

src/include/device/pci_ids.h

@@ -4687,6 +4687,8 @@
 #define PCI_DID_INTEL_WCL_ID_1			0xfd00
 #define PCI_DID_INTEL_WCL_ID_2			0xfd01
 #define PCI_DID_INTEL_WCL_ID_3			0xfd02
+#define PCI_DID_INTEL_WCL_ID_4			0xfd03
+#define PCI_DID_INTEL_WCL_ID_5			0xfd04
 
 /* Intel SMBUS device Ids */
 #define PCI_DID_INTEL_LPT_H_SMBUS			0x8c22

src/mainboard/google/ocelot/variants/baseboard/ocelot/devicetree.cb

@@ -63,6 +63,17 @@ chip soc/intel/pantherlake
 	# Enable Energy Reporting
 	register "pch_pm_energy_report_enable" = "true"
 
+	# Reference: 858124 Power Delivery Guide Rev1p0, 830097 Powermap Rev1p1
+	# fast_vmode_i_trip values are derived from ICCMax with a safety margin.
+	# ITRIP_NOM is approximately 0.70 of ICCMax
+	# TODO: Update with actual i_trip values.
+
+	register "fast_vmode_i_trip[WCL_CORE]" = "{
+		[VR_DOMAIN_IA] = 35 * 4,
+		[VR_DOMAIN_GT] = 35 * 4,
+		[VR_DOMAIN_SA] = 24 * 4
+	}"
+
 	register "serial_io_uart_mode" = "{
 		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
 		[PchSerialIoIndexUART1] = PchSerialIoDisabled,

src/soc/intel/common/block/systemagent/systemagent.c

@@ -428,6 +428,8 @@ static const unsigned short systemagent_ids[] = {
 	PCI_DID_INTEL_WCL_ID_1,
 	PCI_DID_INTEL_WCL_ID_2,
 	PCI_DID_INTEL_WCL_ID_3,
+	PCI_DID_INTEL_WCL_ID_4,
+	PCI_DID_INTEL_WCL_ID_5,
 	PCI_DID_INTEL_PTL_U_ID_1,
 	PCI_DID_INTEL_PTL_U_ID_2,
 	PCI_DID_INTEL_PTL_U_ID_3,

src/soc/intel/pantherlake/bootblock/report_platform.c

@@ -44,6 +44,8 @@ static struct {
 	{ PCI_DID_INTEL_WCL_ID_1, "Wildcatlake" },
 	{ PCI_DID_INTEL_WCL_ID_2, "Wildcatlake" },
 	{ PCI_DID_INTEL_WCL_ID_3, "Wildcatlake" },
+	{ PCI_DID_INTEL_WCL_ID_4, "Wildcatlake" },
+	{ PCI_DID_INTEL_WCL_ID_5, "Wildcatlake" },
 };
 
 static struct {

src/soc/intel/pantherlake/chip.h

@@ -58,6 +58,7 @@ enum soc_intel_pantherlake_power_limits {
 	PTL_H_1_CORE,
 	PTL_H_2_CORE,
 	PTL_H_3_CORE,
+	WCL_CORE,
 	PTL_POWER_LIMITS_COUNT,
 };
 
@@ -74,7 +75,12 @@ enum soc_intel_pantherlake_sku {
 	PTL_H484_SKU,
 	PTL_H4XE_SKU,
 	PTL_H204_SKU,
-	MAX_PTL_SKUS
+	WCL_SKU_1,
+	WCL_SKU_2,
+	WCL_SKU_3,
+	WCL_SKU_4,
+	WCL_SKU_5,
+	MAX_PTL_SKUS,
 };
 
 /* Mapping of different SKUs based on CPU ID and TDP values */
@@ -98,6 +104,11 @@ static const struct soc_intel_pantherlake_power_map {
 	{ PCI_DID_INTEL_PTL_H_ID_6, PTL_H_2_CORE, TDP_25W, PTL_H4XE_SKU },
 	{ PCI_DID_INTEL_PTL_H_ID_7, PTL_H_2_CORE, TDP_25W, PTL_H4XE_SKU },
 	{ PCI_DID_INTEL_PTL_H_ID_8, PTL_H_2_CORE, TDP_25W, PTL_H12XE_SKU },
+	{ PCI_DID_INTEL_WCL_ID_1, WCL_CORE, TDP_15W, WCL_SKU_1},
+	{ PCI_DID_INTEL_WCL_ID_2, WCL_CORE, TDP_15W, WCL_SKU_2},
+	{ PCI_DID_INTEL_WCL_ID_3, WCL_CORE, TDP_15W, WCL_SKU_3},
+	{ PCI_DID_INTEL_WCL_ID_4, WCL_CORE, TDP_15W, WCL_SKU_4},
+	{ PCI_DID_INTEL_WCL_ID_5, WCL_CORE, TDP_15W, WCL_SKU_5},
 };
 
 /* Types of display ports */

src/soc/intel/pantherlake/chipset_wcl.cb

@@ -2,7 +2,11 @@ chip soc/intel/pantherlake
 
 	device cpu_cluster 0 on end
 
-	# TODO: Add WCL power limits
+	register "power_limits_config[WCL_CORE]" = "{
+		.tdp_pl1_override = 15,
+		.tdp_pl2_override = 35,
+		.tdp_pl4 = 93,
+	}"
 
 	# Reduce the size of BasicMemoryTests to speed up the boot time.
 	register "lower_basic_mem_test_size" = "true"