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soc/intel/mtl/romstage/fsp_params.c: Refactor pcie_rp_init()

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Extract the logic to configure PCIe RPs' clock source and clock request
signals to a separate function, so that the loop in `pcie_rp_init()` is
easier to reuse to program other PCIe-related settings.

While we're at it, make a few small improvements such as printing which
RP index is missing the clock structure definition as well as using the
`BIT()` macro (which is already used in `pcie_rp_init()`. Also retype a
few variables for the RP index, as it is never bigger than a `uint8_t`,
the type of the return value of the `get_max_pcie_port()` function.

Change-Id: I5583ef863630790cedd901e7bd30f4606f887a04
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This commit is contained in:
Angel Pons 2025-10-28 13:23:09 +01:00 • committed by Matt DeVillier
commit ec5b5386d4
1 changed files with 26 additions and 21 deletions
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53
src/soc/intel/meteorlake/romstage/fsp_params.c
View file

@ -36,35 +36,40 @@
#define FSP_CLK_LAN 0x70
#define FSP_CLK_FREE_RUNNING 0x80
static void configure_rp_clocks(FSP_M_CONFIG *m_cfg,
const struct pcie_rp_config *rp_cfg,
size_t index)
{
static unsigned int clk_req_mapping = 0;
if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE))
return;
if (rp_cfg->flags & PCIE_RP_CLK_SRC_UNUSED)
return;
if (!rp_cfg->flags && rp_cfg->clk_src == 0 && rp_cfg->clk_req == 0) {
printk(BIOS_WARNING, "Missing root port %zu clock structure definition\n",
index + 1);
return;
}
if (!(rp_cfg->flags & PCIE_RP_CLK_REQ_UNUSED)) {
if (clk_req_mapping & BIT(rp_cfg->clk_req)) {
printk(BIOS_WARNING,
"Found overlapped clkreq assignment on clk req %u\n",
rp_cfg->clk_req);
}
m_cfg->PcieClkSrcClkReq[rp_cfg->clk_src] = rp_cfg->clk_req;
clk_req_mapping |= BIT(rp_cfg->clk_req);
}
m_cfg->PcieClkSrcUsage[rp_cfg->clk_src] = index;
}
static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask,
const struct pcie_rp_config *cfg, size_t cfg_count)
{
size_t i;
static unsigned int clk_req_mapping = 0;
/* Will be refactored to only skip configuring CLKSRC and CLKREQ */
if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE))
return;
for (i = 0; i < cfg_count; i++) {
for (size_t i = 0; i < cfg_count; i++) {
if (!(en_mask & BIT(i)))
continue;
if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED)
continue;
if (!cfg[i].flags && cfg[i].clk_src == 0 && cfg[i].clk_req == 0) {
printk(BIOS_WARNING, "Missing root port clock structure definition\n");
continue;
}
if (!(cfg[i].flags & PCIE_RP_CLK_REQ_UNUSED)) {
if (clk_req_mapping & (1 << cfg[i].clk_req))
printk(BIOS_WARNING,
"Found overlapped clkreq assignment on clk req %u\n",
cfg[i].clk_req);
m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req;
clk_req_mapping |= 1 << cfg[i].clk_req;
}
m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = i;
configure_rp_clocks(m_cfg, &cfg[i], i);
}
}