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soc/intel/pantherlake: Add DDR5 memory type debug message

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This commit introduces a debug message to the DDR5 memory type
initialization process within the Panther Lake SoC. By adding this log,
developers can gain better insights when diagnosing issues related to
DDR5 memory configurations.

BUG=none
TEST=Verify the debug message is displayed during DDR5 initialization.

Change-Id: I77ceea0f7a29983dd2e4ad1af26a0383721d7ca0
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89331
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Bora Guvendik 2025-09-24 11:23:31 -07:00 • committed by Matt DeVillier
commit 15b903e1fd
1 changed files with 1 additions and 0 deletions
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src/soc/intel/pantherlake/meminit.c
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@ -196,6 +196,7 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
switch (mb_cfg->type) {
case MEM_TYPE_DDR5:
printk(BIOS_DEBUG, "%s: module type is DDR5\n", __func__);
meminit_ddr(mem_cfg, &mb_cfg->ddr_config);
dq_dqs_auto_detect = true;
/*