soc/intel/pantherlake: Add VR power state current thresholds
This commit introduces support for configuring power state current thresholds (PS1, PS2, PS3) for each Voltage Regulator (VR) domain in the Panther Lake SoC. The thresholds allow platform integrators to specify current thresholds (in 1/4 A increments, 0-128 A) for each VR domain and power state. A value of 0 indicates AUTO (use default). Change-Id: If4d473901c8de02b3d6cef44f5481a1864f14d63 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Cliff Huang <cliff.huang@intel.com>
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2 changed files with 23 additions and 0 deletions
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@ -457,6 +457,20 @@ struct soc_intel_pantherlake_config {
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*/
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uint16_t icc_max[MAX_PTL_SKUS][NUM_VR_DOMAINS];
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/*
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* Power State Current Thresholds for VR Domains.
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*
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* These arrays define the current thresholds for different power states (PS1,
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* PS2, PS3) for each Voltage Regulator (VR) domain.
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*
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* Each value is defined in 1/4 A increments. For example, a value of 400
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* corresponds to 100A. The valid range is 0-512 (0-128A). A value of 0
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* indicates AUTO (use default).
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*/
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uint16_t ps1_threshold[NUM_VR_DOMAINS];
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uint16_t ps2_threshold[NUM_VR_DOMAINS];
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uint16_t ps3_threshold[NUM_VR_DOMAINS];
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/*
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* SerialIO device mode selection:
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* PchSerialIoDisabled,
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@ -357,6 +357,15 @@ static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg,
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m_cfg->TdcMode[i] = config->tdc_mode[i];
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m_cfg->TdcTimeWindow[i] = config->tdc_time_window_ms[i];
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}
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for (size_t i = 0; i < ARRAY_SIZE(config->ps1_threshold); i++) {
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if (config->ps1_threshold[i])
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m_cfg->Ps1Threshold[i] = config->ps1_threshold[i];
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if (config->ps2_threshold[i])
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m_cfg->Ps2Threshold[i] = config->ps2_threshold[i];
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if (config->ps3_threshold[i])
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m_cfg->Ps3Threshold[i] = config->ps3_threshold[i];
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}
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}
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#if CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR)
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