soc/intel/common/block/pcie: Move speed helper to pcie_helpers.c

The pcie_speed_control_to_upd() helper function was only available in
aspm.c for PCH root port configuration. However, CPU root ports in
romstage also need to convert PCIE_SPEED_control enum values to FSP
UPD indices.

Move pcie_speed_control_to_upd() from aspm.c to pcie_helpers.c to
make it available in both romstage and ramstage. This allows both
PCH and CPU root port code to use the same conversion logic without
code duplication.

The helper handles the mapping between devicetree enum values and FSP
UPD values using the UPD_INDEX() macro (which subtracts 1):
- SPEED_DEFAULT (0) -> SPEED_AUTO (1) -> UPD_INDEX = 0
- SPEED_AUTO (1) -> UPD_INDEX = 0
- SPEED_GEN1 (2) -> UPD_INDEX = 1
- SPEED_GEN2 (3) -> UPD_INDEX = 2
- SPEED_GEN3 (4) -> UPD_INDEX = 3
- SPEED_GEN4 (5) -> UPD_INDEX = 4

This accounts for the fact that FSP expects 0-based indexing where
0 = Auto, 1 = Gen1, 2 = Gen2, etc.

TEST=Configured PCIE_SPEED_GEN2 for root port on mc_rpl1, booted and
verified with lspci -vv that device is limited to Gen2 speed

Change-Id: I0f70ad4da6f9f9e73b1c05648f0b206d5d61e07d
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/soc/intel/common/block/aspm/aspm.c

@@ -74,15 +74,6 @@ static unsigned int l1ss_control_to_upd(enum L1_substates_control l1_substates_c
 	return UPD_INDEX(l1_substates_control);
 }
 
-static unsigned int pcie_speed_control_to_upd(enum PCIE_SPEED_control pcie_speed_control)
-{
-	/* Use auto unless overwritten */
-	if (!pcie_speed_control)
-		return UPD_INDEX(SPEED_AUTO);
-
-	return UPD_INDEX(pcie_speed_control);
-}
-
 void configure_pch_rp_power_management(FSP_S_CONFIG *s_cfg,
 					      const struct pcie_rp_config *rp_cfg,
 					      unsigned int index)

src/soc/intel/common/block/include/intelblocks/pcie_rp.h

@@ -149,6 +149,19 @@ void pcie_rp_update_devicetree(const struct pcie_rp_group *groups);
  */
 uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *groups);
 
+/*
+ * Convert PCIe speed control setting to UPD index format.
+ *
+ * Takes a PCIE_SPEED_control enum value and converts it to the corresponding
+ * UPD (Unit Parameter Data) index required by the firmware interface.
+ *
+ * If pcie_speed_control is 0 (uninitialized/default), the function returns
+ * the UPD index for SPEED_AUTO, enabling automatic speed negotiation.
+ * Otherwise, it returns the UPD index corresponding to the specified speed
+ * control value.
+ */
+unsigned int pcie_speed_control_to_upd(enum PCIE_SPEED_control pcie_speed_control);
+
 /* Get PCH root port groups */
 const struct pcie_rp_group *soc_get_pch_rp_groups(void);
 

src/soc/intel/common/block/pcie/pcie_helpers.c

@@ -39,3 +39,12 @@ uint32_t pcie_rp_enable_mask(const struct pcie_rp_group *const groups)
 
 	return mask;
 }
+
+unsigned int pcie_speed_control_to_upd(enum PCIE_SPEED_control pcie_speed_control)
+{
+	/* Use auto unless overwritten */
+	if (!pcie_speed_control)
+		return UPD_INDEX(SPEED_AUTO);
+
+	return UPD_INDEX(pcie_speed_control);
+}