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soc/intel/{adl,mtl}: Fix CLKSRC handling for compliance mode

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The code was indexing an array of clock sources using an RP index which
is not correct. As the intent of compliance mode seems to be to set all
clock sources to be free-running, do the same from a different place in
order to avoid potential out-of-bounds accesses.

To preserve original behaviour, exit early from `pcie_rp_init()`. While
this is rather crude, subsequent commits will refactor said function.

Change-Id: I89e6e9f85b7b86b0a74ece88641a378f2c0b599f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89788
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This commit is contained in:
Angel Pons 2025-10-28 12:49:19 +01:00 • committed by Matt DeVillier
commit c917ecf21e
2 changed files with 14 additions and 10 deletions
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12
src/soc/intel/alderlake/romstage/fsp_params.c
View file

@ -62,11 +62,11 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, enum pcie_rp_typ
/* bitmask to save the status of clkreq assignment */
static unsigned int clk_req_mapping = 0;
/* Will be refactored to only skip configuring CLKSRC and CLKREQ */
if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE))
return;
for (i = 0; i < cfg_count; i++) {
if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) {
m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING;
continue;
}
if (!(en_mask & BIT(i)))
continue;
if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED)
@ -95,7 +95,9 @@ static void fill_fspm_pcie_rp_params(FSP_M_CONFIG *m_cfg,
unsigned int i;
for (i = 0; i < CONFIG_MAX_PCIE_CLOCK_SRC; i++) {
if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING)
if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE))
m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING;
else if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING)
m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING;
else if (config->pcie_clk_config_flag[i] & PCIE_CLK_LAN)
m_cfg->PcieClkSrcUsage[i] = FSP_CLK_LAN;

12
src/soc/intel/meteorlake/romstage/fsp_params.c
View file

@ -42,11 +42,11 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask,
size_t i;
static unsigned int clk_req_mapping = 0;
/* Will be refactored to only skip configuring CLKSRC and CLKREQ */
if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE))
return;
for (i = 0; i < cfg_count; i++) {
if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE)) {
m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING;
continue;
}
if (!(en_mask & BIT(i)))
continue;
if (cfg[i].flags & PCIE_RP_CLK_SRC_UNUSED)
@ -76,7 +76,9 @@ static void fill_fspm_pcie_rp_params(FSP_M_CONFIG *m_cfg,
uint8_t max_clock = get_max_pcie_clock();
for (i = 0; i < max_clock; i++) {
if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING)
if (CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE))
m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING;
else if (config->pcie_clk_config_flag[i] & PCIE_CLK_FREE_RUNNING)
m_cfg->PcieClkSrcUsage[i] = FSP_CLK_FREE_RUNNING;
else if (config->pcie_clk_config_flag[i] & PCIE_CLK_LAN)
m_cfg->PcieClkSrcUsage[i] = FSP_CLK_LAN;