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soc/intel/alderlake: Make CPU RP PCIe speed configurable

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Add PCIe speed configuration for CPU root ports in FSP-M. Previously,
only PCH root port speed could be configured via FSP-S. Since CPU root
ports are initialized in FSP-M, they require configuration during
romstage.

This change uses the pcie_speed_control_to_upd() helper (now available
in the shared header) to convert devicetree PCIE_SPEED_control values
to FSP UPD indices. The configuration respects the pciexp_speed CMOS
option override if present, otherwise uses the devicetree setting.

TEST=Booted on mc_rpl1. Configured CPU RP to different PCIe speeds
(Gen1/Gen2/Gen3) via devicetree and verified correct link speed
negotiation with lspci for each configuration.

Change-Id: If3d871f238e7f063fef01c68cc371ae72ec9642c
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Kilian Krause 2025-10-27 10:04:56 +01:00 • committed by Matt DeVillier
commit fad0908c5b
1 changed files with 15 additions and 0 deletions
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15
src/soc/intel/alderlake/romstage/fsp_params.c
View file

@ -55,6 +55,19 @@ static uint8_t clk_src_to_fsp(enum pcie_rp_type type, int rp_number)
return CPU_PCIE_BASE + rp_number;
}
static void configure_cpu_rp_speed(FSP_M_CONFIG *m_cfg,
const struct pcie_rp_config *cfg,
size_t index)
{
static const char *const speeds[] = {"AUTO", "GEN1", "GEN2", "GEN3", "GEN4"};
m_cfg->CpuPcieRpPcieSpeed[index] =
pcie_speed_control_to_upd(get_uint_option("pciexp_speed",
cfg->pcie_rp_pcie_speed));
printk(BIOS_DEBUG, "CPU PCIe RP%zu: speed set to %s\n",
index + 1, speeds[m_cfg->CpuPcieRpPcieSpeed[index]]);
}
static void configure_rp_clocks(FSP_M_CONFIG *m_cfg, enum pcie_rp_type type,
const struct pcie_rp_config *rp_cfg, size_t index)
{
@ -89,6 +102,8 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, enum pcie_rp_typ
if (!(en_mask & BIT(i)))
continue;
configure_rp_clocks(m_cfg, type, &cfg[i], i);
if (type == PCIE_RP_CPU)
configure_cpu_rp_speed(m_cfg, &cfg[i], i);
}
}