src/soc/intel/ptl: Add LPSS UART DMA control

This patch implements passing a "SerialIoUartDmaEnable" pointer to
FSP-S by parsing the devicetree.

Default (0) means PIO, while 1 means DMA.

Change-Id: Id0acfe0b30899a3019ea7e54067fc06cbc56bab6
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>

src/soc/intel/pantherlake/chip.h

@@ -483,12 +483,21 @@ struct soc_intel_pantherlake_config {
 	uint8_t serial_io_i2c_mode[CONFIG_SOC_INTEL_I2C_DEV_MAX];
 	uint8_t serial_io_gspi_mode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
 	uint8_t serial_io_uart_mode[CONFIG_SOC_INTEL_UART_DEV_MAX];
+
+	/*
+	 * SerialIO DMA/PIO mode:
+	 * 0: Disable (PIO)
+	 * 1: Enable (DMA)
+	 */
+	uint8_t serial_io_uart_dma_enable[CONFIG_SOC_INTEL_UART_DEV_MAX];
+
 	/*
 	 * GSPIn Default Chip Select Mode:
 	 * 0:Hardware Mode,
 	 * 1:Software Mode
 	 */
 	uint8_t serial_io_gspi_cs_mode[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
+
 	/*
 	 * GSPIn Default Chip Select State:
 	 * 0: Low,

src/soc/intel/pantherlake/fsp_params.c

@@ -289,6 +289,8 @@ static void fill_fsps_lpss_params(FSP_S_CONFIG *s_cfg,
 			config->serial_io_uart_mode[i] : 0;
 		s_cfg->SerialIoUartPowerGating[i] = is_devfn_enabled(uart_dev[i]) ?
 			LPSS_UART_PG_ENABLED : LPSS_UART_PG_AUTO;
+		s_cfg->SerialIoUartDmaEnable[i] = is_devfn_enabled(uart_dev[i]) ?
+			config->serial_io_uart_dma_enable[i] : 0;
 	}
 }
 

src/soc/intel/pantherlake/include/soc/serialio.h

@@ -11,6 +11,11 @@ enum {
 	PchSerialIoSkipInit
 };
 
+enum {
+	PchSerialPio,
+	PchSerialDma
+};
+
 enum {
 	PchSerialIoIndexI2C0,
 	PchSerialIoIndexI2C1,