tree: Use boolean for s3resume

Change-Id: I3e23134f879fcaf817cf62b641e9b59563eb643b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>

src/arch/arm64/include/arch/acpi.h

@@ -5,8 +5,8 @@
 
 /* STUB */
 
-static inline int acpi_is_wakeup(void) { return 0; }
-static inline int acpi_is_wakeup_s3(void) { return 0; }
-static inline int acpi_is_wakeup_s4(void) { return 0; }
+static inline bool acpi_is_wakeup(void) { return false; }
+static inline bool acpi_is_wakeup_s3(void) { return false; }
+static inline bool acpi_is_wakeup_s4(void) { return false; }
 
 #endif  /* __ARCH_ACPI_H_ */

src/drivers/amd/agesa/mtrr_fixme.c

@@ -33,7 +33,7 @@ static void set_range_uc(u32 base, u32 size)
 	wrmsr(MTRR_PHYS_MASK(i), msr);
 }
 
-void fixup_cbmem_to_UC(int s3resume)
+void fixup_cbmem_to_UC(bool s3resume)
 {
 	if (s3resume)
 		return;
@@ -54,7 +54,7 @@ static void recover_postcar_frame(struct postcar_frame *pcf)
 {
 	msr_t base, mask;
 	int i;
-	int s3resume = romstage_handoff_is_resume();
+	bool s3resume = romstage_handoff_is_resume();
 
 	/* Replicate non-UC MTRRs as left behind by AGESA.
 	 */

src/drivers/tpm/tpm.c

@@ -6,7 +6,7 @@
 
 static void init_tpm_dev(void *unused)
 {
-	int s3resume = acpi_is_wakeup_s3();
+	bool s3resume = acpi_is_wakeup_s3();
 	tpm_setup(s3resume);
 }
 

src/include/acpi/acpi.h

@@ -1975,10 +1975,10 @@ static inline bool acpi_s3_resume_allowed(void)
 	return CONFIG(HAVE_ACPI_RESUME);
 }
 
-static inline int acpi_is_wakeup_s3(void)
+static inline bool acpi_is_wakeup_s3(void)
 {
 	if (!acpi_s3_resume_allowed())
-		return 0;
+		return false;
 
 	if (ENV_ROMSTAGE_OR_BEFORE)
 		return (acpi_get_sleep_type() == ACPI_S3);

src/include/cbmem.h

@@ -6,6 +6,7 @@
 #include <commonlib/bsd/cbmem_id.h> /* IWYU pragma: export */
 #include <stddef.h>
 #include <stdint.h>
+#include <stdbool.h>
 #include <boot/coreboot_tables.h>
 
 #define CBMEM_FSP_HOB_PTR	0x614
@@ -86,7 +87,7 @@ u64 cbmem_entry_size(const struct cbmem_entry *entry);
 
 /* Returns 0 if old cbmem was recovered. Recovery is only attempted if
  * s3resume is non-zero. */
-int cbmem_recovery(int s3resume);
+int cbmem_recovery(bool s3resume);
 /* Add a cbmem entry of a given size and id. These return NULL on failure. The
  * add function performs a find first and do not check against the original
  * size. */

src/include/romstage_handoff.h

@@ -2,10 +2,11 @@
 #ifndef ROMSTAGE_HANDOFF_H
 #define ROMSTAGE_HANDOFF_H
 
+#include <stdbool.h>
+
 /* Returns 0 if initialized. Else < 0 if handoff structure not added. */
 int romstage_handoff_init(int is_s3_resume);
 
-/* Return 1 if resuming or 0 if not. */
-int romstage_handoff_is_resume(void);
+bool romstage_handoff_is_resume(void);
 
 #endif /* ROMSTAGE_HANDOFF_H */

src/include/stage_cache.h

@@ -39,10 +39,10 @@ static inline void stage_cache_get_raw(int stage_id, void **base, size_t *size)
 
 #endif
 
-static inline int resume_from_stage_cache(void)
+static inline bool resume_from_stage_cache(void)
 {
 	if (CONFIG(NO_STAGE_CACHE))
-		return 0;
+		return false;
 
 	/* TBD: Replace this with acpi_is_wakeup_s3(). */
 	return romstage_handoff_is_resume();

src/lib/bootblock.c

@@ -59,7 +59,7 @@ void bootblock_main_with_timestamp(uint64_t base_timestamp,
 	bootblock_mainboard_init();
 
 	if (CONFIG(TPM_MEASURED_BOOT_INIT_BOOTBLOCK)) {
-		int s3resume = acpi_is_wakeup_s3();
+		bool s3resume = acpi_is_wakeup_s3();
 		tpm_setup(s3resume);
 	}
 

src/lib/imd_cbmem.c

@@ -121,7 +121,7 @@ int cbmem_initialize_id_size(u32 id, u64 size)
 	return 0;
 }
 
-int cbmem_recovery(int is_wakeup)
+int cbmem_recovery(bool is_wakeup)
 {
 	int rv = 0;
 	if (!is_wakeup)

src/lib/romstage_handoff.c

@@ -53,19 +53,19 @@ int romstage_handoff_init(int is_s3_resume)
 	return 0;
 }
 
-int romstage_handoff_is_resume(void)
+bool romstage_handoff_is_resume(void)
 {
-	static int once, s3_resume;
+	static bool once, s3_resume;
 	struct romstage_handoff *handoff;
 
 	if (once)
 		return s3_resume;
 
 	/* Only try evaluate handoff once for s3 resume state. */
-	once = 1;
+	once = true;
 	handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO);
 	if (handoff == NULL)
-		return 0;
+		return false;
 
 	s3_resume = handoff->s3_resume;
 	if (s3_resume)

src/mainboard/dell/snb_ivb_workstations/romstage.c

@@ -23,7 +23,7 @@ void mainboard_late_rcba_config(void)
 	DIR_ROUTE(D20IR, PIRQA, PIRQB, PIRQC, PIRQD);
 }
 
-void mainboard_early_init(int s3resume)
+void mainboard_early_init(bool s3resume)
 {
 	uint16_t ec_fw_version;
 

src/mainboard/emulation/qemu-i440fx/romstage.c

@@ -5,5 +5,5 @@
 
 void mainboard_romstage_entry(void)
 {
-	cbmem_recovery(0);
+	cbmem_recovery(false);
 }

src/mainboard/emulation/qemu-q35/romstage.c

@@ -29,5 +29,5 @@ void mainboard_romstage_entry(void)
 		printk(BIOS_WARNING, "%s: Unsupported TSEG size: 0x%x\n", __func__, CONFIG_SMM_TSEG_SIZE);
 	}
 
-	cbmem_recovery(0);
+	cbmem_recovery(false);
 }

src/mainboard/google/auron/ec.c

@@ -14,7 +14,7 @@ void mainboard_ec_init(void)
 		.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
 	};
 
-	int s3_wakeup = acpi_is_wakeup_s3();
+	bool s3_wakeup = acpi_is_wakeup_s3();
 
 	printk(BIOS_DEBUG, "%s\n", __func__);
 	post_code(0xf0);

src/mainboard/google/auron/variants/gandof/variant.c

@@ -24,7 +24,7 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current)
 	return len;
 }
 
-void mainboard_post_raminit(const int s3resume)
+void mainboard_post_raminit(const bool s3resume)
 {
 	if (!s3resume)
 		google_chromeec_kbbacklight(75);

src/mainboard/google/auron/variants/lulu/variant.c

@@ -34,7 +34,7 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current)
 	return len;
 }
 
-void mainboard_post_raminit(const int s3resume)
+void mainboard_post_raminit(const bool s3resume)
 {
 	if (!s3resume)
 		google_chromeec_kbbacklight(75);

src/mainboard/google/auron/variants/samus/variant.c

@@ -21,7 +21,7 @@ int variant_smbios_data(struct device *dev, int *handle, unsigned long *current)
 	return 0;
 }
 
-void mainboard_post_raminit(const int s3resume)
+void mainboard_post_raminit(const bool s3resume)
 {
 	if (!s3resume)
 		google_chromeec_kbbacklight(100);

src/mainboard/google/link/early_init.c

@@ -71,7 +71,7 @@ void mb_get_spd_map(struct spd_info *spdi)
 	spdi->spd_index = get_spd_index();
 }
 
-void mainboard_early_init(int s3resume)
+void mainboard_early_init(bool s3resume)
 {
 	if (!s3resume) {
 		/* This is the fastest way to let users know

src/mainboard/google/slippy/ec.c

@@ -14,7 +14,7 @@ void mainboard_ec_init(void)
 		.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
 	};
 
-	int s3_wakeup = acpi_is_wakeup_s3();
+	bool s3_wakeup = acpi_is_wakeup_s3();
 
 	printk(BIOS_DEBUG, "%s\n", __func__);
 	post_code(0xf0);

src/mainboard/google/stout/early_init.c

@@ -83,7 +83,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 	/* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
 }
 
-void mainboard_early_init(int s3resume)
+void mainboard_early_init(bool s3resume)
 {
 	/* Do ec reset as early as possible, but skip it on S3 resume */
 	if (!s3resume) {

src/mainboard/kontron/ktqm77/early_init.c

@@ -54,7 +54,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
 }
 
-void mainboard_early_init(int s3resume)
+void mainboard_early_init(bool s3resume)
 {
 	/* Enable PEG10 (1x16) */
 	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN,

src/mainboard/lenovo/t420/early_init.c

@@ -30,7 +30,7 @@ static void hybrid_graphics_init(void)
 	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
 }
 
-void mainboard_early_init(int s3resume)
+void mainboard_early_init(bool s3resume)
 {
 	hybrid_graphics_init();
 }

src/mainboard/lenovo/t420s/early_init.c

@@ -30,7 +30,7 @@ static void hybrid_graphics_init(void)
 	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
 }
 
-void mainboard_early_init(int s3resume)
+void mainboard_early_init(bool s3resume)
 {
 	hybrid_graphics_init();
 }

src/mainboard/lenovo/t430/early_init.c

@@ -32,7 +32,7 @@ static void hybrid_graphics_init(void)
 	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
 }
 
-void mainboard_early_init(int s3resume)
+void mainboard_early_init(bool s3resume)
 {
 	hybrid_graphics_init();
 }

src/mainboard/lenovo/t430s/variants/t430s/romstage.c

@@ -7,7 +7,7 @@
 #include <ec/lenovo/pmh7/pmh7.h>
 #include <types.h>
 
-void mainboard_early_init(int s3resume)
+void mainboard_early_init(bool s3resume)
 {
 	u8 enable_peg = get_uint_option("enable_dual_graphics", 0);
 

src/mainboard/lenovo/t520/early_init.c

@@ -34,7 +34,7 @@ static void hybrid_graphics_init(void)
 	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
 }
 
-void mainboard_early_init(int s3resume)
+void mainboard_early_init(bool s3resume)
 {
 	hybrid_graphics_init();
 }

src/mainboard/lenovo/t530/early_init.c

@@ -33,7 +33,7 @@ static void hybrid_graphics_init(void)
 	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
 }
 
-void mainboard_early_init(int s3resume)
+void mainboard_early_init(bool s3resume)
 {
 	hybrid_graphics_init();
 }

src/mainboard/supermicro/x9scl/early_init.c

@@ -83,7 +83,7 @@ void bootblock_mainboard_early_init(void)
 	bmc_init();
 }
 
-void mainboard_early_init(int s3resume)
+void mainboard_early_init(bool s3resume)
 {
 	/* Disable IGD VGA decode, no GTT or GFX stolen */
 	pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2);

src/northbridge/amd/agesa/agesa_helper.h

@@ -34,7 +34,7 @@ void EmptyHeap(void);
 
 #define HIGH_MEMORY_SCRATCH		0x30000
 
-void fixup_cbmem_to_UC(int s3resume);
+void fixup_cbmem_to_UC(bool s3resume);
 
 void restore_mtrr(void);
 void backup_mtrr(void);

src/northbridge/amd/agesa/state_machine.h

@@ -3,6 +3,7 @@
 #ifndef _STATE_MACHINE_H_
 #define _STATE_MACHINE_H_
 
+#include <stdbool.h>
 #include <stdint.h>
 #include <AGESA.h>
 #include <AMD.h>
@@ -28,7 +29,7 @@ struct sysinfo
 {
 	AMD_CONFIG_PARAMS StdHeader;
 
-	int s3resume;
+	bool s3resume;
 };
 
 void board_BeforeAgesa(struct sysinfo *cb);

src/northbridge/intel/e7505/romstage.c

@@ -14,5 +14,5 @@ void mainboard_romstage_entry(void)
 
 	sdram_initialize();
 
-	cbmem_recovery(0);
+	cbmem_recovery(false);
 }

src/northbridge/intel/gm45/gm45.h

@@ -410,7 +410,7 @@ void gm45_early_reset(void);
 
 void enter_raminit_or_reset(void);
 void get_gmch_info(sysinfo_t *);
-void raminit(sysinfo_t *, int s3resume);
+void raminit(sysinfo_t *, bool s3resume);
 void raminit_thermal(const sysinfo_t *);
 void setup_sdram_meminfo(const sysinfo_t *);
 void init_igd(const sysinfo_t *const);
@@ -423,8 +423,8 @@ u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank);
 void raminit_rcomp_calibration(stepping_t stepping);
 void raminit_reset_readwrite_pointers(void);
 void raminit_receive_enable_calibration(int ddr_type, const timings_t *, const dimminfo_t *);
-void raminit_write_training(const mem_clock_t, const dimminfo_t *, int s3resume);
-void raminit_read_training(const dimminfo_t *, int s3resume);
+void raminit_write_training(const mem_clock_t, const dimminfo_t *, bool s3resume);
+void raminit_read_training(const dimminfo_t *, bool s3resume);
 
 void gm45_late_init(stepping_t);
 

src/northbridge/intel/gm45/raminit.c

@@ -2100,7 +2100,7 @@ void raminit_reset_readwrite_pointers(void)
 	mchbar_setbits32(0x15f0, 1 << 10);
 }
 
-void raminit(sysinfo_t *const sysinfo, const int s3resume)
+void raminit(sysinfo_t *const sysinfo, const bool s3resume)
 {
 	const dimminfo_t *const dimms = sysinfo->dimms;
 	const timings_t *const timings = &sysinfo->selected_timings;

src/northbridge/intel/gm45/raminit_read_write_training.c

@@ -262,7 +262,7 @@ static void read_training_restore_results(void)
 		}
 	}
 }
-void raminit_read_training(const dimminfo_t *const dimms, const int s3resume)
+void raminit_read_training(const dimminfo_t *const dimms, const bool s3resume)
 {
 	if (!s3resume) {
 		perform_read_training(dimms);
@@ -633,7 +633,7 @@ static void write_training_restore_results(const int memclk1067)
 }
 void raminit_write_training(const mem_clock_t ddr3clock,
 			    const dimminfo_t *const dimms,
-			    const int s3resume)
+			    const bool s3resume)
 {
 	const int memclk1067 = ddr3clock == MEM_CLOCK_1067MT;
 

src/northbridge/intel/gm45/romstage.c

@@ -33,7 +33,7 @@ void __weak mb_post_raminit_setup(void)
 void mainboard_romstage_entry(void)
 {
 	sysinfo_t sysinfo;
-	int s3resume = 0;
+	bool s3resume = false;
 	int cbmem_initted;
 	u16 reg16;
 

src/northbridge/intel/haswell/broadwell_mrc/raminit.c

@@ -310,7 +310,7 @@ static uint8_t map_to_pei_oc_pin(const uint8_t oc_pin)
 	return oc_pin >= USB_OC_PIN_SKIP ? PEI_USB_OC_PIN_SKIP : oc_pin;
 }
 
-static bool early_init_native(int s3resume)
+static bool early_init_native(bool s3resume)
 {
 	printk(BIOS_DEBUG, "Starting native platform initialisation\n");
 
@@ -326,7 +326,7 @@ static bool early_init_native(int s3resume)
 	return cpu_replaced;
 }
 
-void perform_raminit(const int s3resume)
+void perform_raminit(const bool s3resume)
 {
 	const struct northbridge_intel_haswell_config *cfg = config_of_soc();
 

src/northbridge/intel/haswell/haswell_mrc/raminit.c

@@ -340,7 +340,7 @@ static uint8_t map_to_pei_oc_pin(const uint8_t oc_pin)
 	return oc_pin >= USB_OC_PIN_SKIP ? PEI_USB_OC_PIN_SKIP : oc_pin;
 }
 
-void perform_raminit(const int s3resume)
+void perform_raminit(const bool s3resume)
 {
 	const struct device *gbe = pcidev_on_root(0x19, 0);
 

src/northbridge/intel/haswell/native_raminit/raminit_native.c

@@ -163,7 +163,7 @@ static enum raminit_boot_mode do_actual_raminit(
 	return bootmode;
 }
 
-void perform_raminit(const int s3resume)
+void perform_raminit(const bool s3resume)
 {
 	/*
 	 * See, this function's name is a lie. There are more things to

src/northbridge/intel/haswell/raminit.h

@@ -17,6 +17,6 @@ struct spd_info {
 void mb_get_spd_map(struct spd_info *spdi);
 
 void get_spd_info(struct spd_info *spdi, const struct northbridge_intel_haswell_config *cfg);
-void perform_raminit(const int s3resume);
+void perform_raminit(const bool s3resume);
 
 #endif	/* NORTHBRIDGE_INTEL_HASWELL_RAMINIT_H */

src/northbridge/intel/haswell/romstage.c

@@ -27,7 +27,7 @@ void mainboard_romstage_entry(void)
 	haswell_early_initialization();
 	printk(BIOS_DEBUG, "Back from haswell_early_initialization()\n");
 
-	const int s3resume = southbridge_detect_s3_resume();
+	const bool s3resume = southbridge_detect_s3_resume();
 
 	elog_boot_notify(s3resume);
 

src/northbridge/intel/i440bx/raminit.c

@@ -989,7 +989,7 @@ static void sdram_enable(void)
 /* Implemented under mainboard. */
 void __weak enable_spd(void) { }
 
-void sdram_initialize(int s3resume)
+void sdram_initialize(bool s3resume)
 {
 	timestamp_add_now(TS_INITRAM_START);
 	enable_spd();

src/northbridge/intel/i440bx/raminit.h

@@ -3,6 +3,8 @@
 #ifndef RAMINIT_H
 #define RAMINIT_H
 
+#include <stdbool.h>
+
 /* The 440BX supports up to four (single- or double-sided) DIMMs. */
 #define DIMM_SOCKETS	4
 
@@ -13,7 +15,7 @@
 #define DIMM3		0x53
 
 void enable_spd(void);
-void sdram_initialize(int s3resume);
+void sdram_initialize(bool s3resume);
 
 /* Debug */
 #if CONFIG(DEBUG_RAM_SETUP)

src/northbridge/intel/i945/early_init.c

@@ -793,16 +793,16 @@ void i945_early_initialization(void)
 	RCBA32(0x2010) |= (1 << 10);
 }
 
-static void i945_prepare_resume(int s3resume)
+static void i945_prepare_resume(bool s3resume)
 {
-	int cbmem_was_initted;
+	bool cbmem_was_initted;
 
 	cbmem_was_initted = !cbmem_recovery(s3resume);
 
 	romstage_handoff_init(cbmem_was_initted && s3resume);
 }
 
-void i945_late_initialization(int s3resume)
+void i945_late_initialization(bool s3resume)
 {
 	i945_setup_egress_port();
 

src/northbridge/intel/i945/i945.h

@@ -323,7 +323,7 @@
 
 int i945_silicon_revision(void);
 void i945_early_initialization(void);
-void i945_late_initialization(int s3resume);
+void i945_late_initialization(bool s3resume);
 
 /* debugging functions */
 void print_pci_devices(void);

src/northbridge/intel/i945/romstage.c

@@ -26,7 +26,7 @@ __weak void mainboard_get_spd_map(u8 spd_map[4])
 
 void mainboard_romstage_entry(void)
 {
-	int s3resume = 0;
+	bool s3resume = false;
 	u8 spd_map[4] = {};
 
 	mainboard_lpc_decode();

src/northbridge/intel/ironlake/quickpath.c

@@ -353,7 +353,7 @@ set_2dx8_reg(struct raminfo *info, u16 reg, u8 mode, u16 freq1, u16 freq2,
 	}
 }
 
-static void set_2dxx_series(struct raminfo *info, int s3resume)
+static void set_2dxx_series(struct raminfo *info, bool s3resume)
 {
 	set_2dx8_reg(info, 0x2d00, 0, 0x78, frequency_11(info) / 2, 1359, 1005,
 		     0, 1);
@@ -573,7 +573,7 @@ void early_quickpath_init(struct raminfo *info, const u8 x2ca8)
 	mchbar_write32(0x18ac, 0x22222);
 }
 
-void late_quickpath_init(struct raminfo *info, const int s3resume)
+void late_quickpath_init(struct raminfo *info, const bool s3resume)
 {
 	const u16 deven = pci_read_config16(NORTHBRIDGE, DEVEN);
 

src/northbridge/intel/ironlake/raminit.c

@@ -333,7 +333,7 @@ static int count_ranks_in_channel(struct raminfo *info, int channel)
 }
 
 static void
-config_rank(struct raminfo *info, int s3resume, int channel, int slot, int rank)
+config_rank(struct raminfo *info, bool s3resume, int channel, int slot, int rank)
 {
 	int add;
 
@@ -2856,7 +2856,7 @@ static void dmi_setup(void)
 	gav(inb(DEFAULT_GPIOBASE | 0xe));	// = 0xfdcaff6e
 }
 
-void chipset_init(const int s3resume)
+void chipset_init(const bool s3resume)
 {
 	u8 x2ca8;
 	u16 ggc;
@@ -2915,12 +2915,12 @@ static u8 get_bits_420(const u32 reg32)
 	return val;
 }
 
-void raminit(const int s3resume, const u8 *spd_addrmap)
+void raminit(const bool s3resume, const u8 *spd_addrmap)
 {
 	unsigned int channel, slot, lane, rank;
 	struct raminfo info;
 	u8 x2ca8;
-	int cbmem_wasnot_inited;
+	bool cbmem_wasnot_inited;
 
 	x2ca8 = mchbar_read8(0x2ca8);
 

src/northbridge/intel/ironlake/raminit.h

@@ -92,7 +92,7 @@ static inline unsigned int frequency_11(struct raminfo *info)
 	return (info->clock_speed_index + 3) * 120;
 }
 
-void chipset_init(const int s3resume);
+void chipset_init(const bool s3resume);
 /* spd_addrmap is array of 4 elements:
    Channel 0 Slot 0
    Channel 0 Slot 1
@@ -100,10 +100,10 @@ void chipset_init(const int s3resume);
    Channel 1 Slot 1
    0 means "not present"
 */
-void raminit(const int s3resume, const u8 *spd_addrmap);
+void raminit(const bool s3resume, const u8 *spd_addrmap);
 
 u16 get_max_timing(struct raminfo *info, int channel);
 void early_quickpath_init(struct raminfo *info, const u8 x2ca8);
-void late_quickpath_init(struct raminfo *info, const int s3resume);
+void late_quickpath_init(struct raminfo *info, const bool s3resume);
 
 #endif				/* RAMINIT_H */

src/northbridge/intel/ironlake/romstage.c

@@ -22,7 +22,7 @@
  */
 void mainboard_romstage_entry(void)
 {
-	int s3resume = 0;
+	bool s3resume = false;
 	u8 spd_addrmap[4] = {};
 
 	/* TODO, make this configurable */
@@ -34,7 +34,7 @@ void mainboard_romstage_entry(void)
 	if (s3resume) {
 		u8 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
 		if (!(reg8 & 0x20)) {
-			s3resume = 0;
+			s3resume = false;
 			printk(BIOS_DEBUG, "Bad resume from S3 detected.\n");
 		}
 	}

src/northbridge/intel/pineview/romstage.c

@@ -27,8 +27,9 @@ __weak void mb_pirq_setup(void)
 void mainboard_romstage_entry(void)
 {
 	u8 spd_addrmap[4] = {};
-	int boot_path, cbmem_was_initted;
-	int s3resume = 0;
+	int boot_path;
+	bool cbmem_was_initted;
+	bool s3resume = false;
 
 	/* Do some early chipset init, necessary for RAM init to work */
 	i82801gx_early_init();

src/northbridge/intel/sandybridge/raminit.c

@@ -341,9 +341,10 @@ static void reinit_ctrl(ramctr_timing *ctrl, const u32 cpuid)
 			ctrl->ecc_forced ? "yes" : "no");
 }
 
-static void init_dram_ddr3(int s3resume, const u32 cpuid)
+static void init_dram_ddr3(bool s3resume, const u32 cpuid)
 {
-	int me_uma_size, cbmem_was_inited, fast_boot, err;
+	int me_uma_size, fast_boot, err;
+	bool cbmem_was_inited;
 	ramctr_timing ctrl;
 	spd_ddr3_raw_data spds[4];
 	size_t mrc_size = 0;
@@ -527,7 +528,7 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid)
 		setup_sdram_meminfo(&ctrl);
 }
 
-void perform_raminit(int s3resume)
+void perform_raminit(bool s3resume)
 {
 	post_code(0x3a);
 	init_dram_ddr3(s3resume, cpu_get_cpuid());

src/northbridge/intel/sandybridge/raminit_common.h

@@ -468,7 +468,7 @@ void set_read_write_timings(ramctr_timing *ctrl);
 void set_normal_operation(ramctr_timing *ctrl);
 void final_registers(ramctr_timing *ctrl);
 void restore_timings(ramctr_timing *ctrl);
-int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size);
+int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, bool s3resume, int me_uma_size);
 
 void channel_scrub(ramctr_timing *ctrl);
 bool get_host_ecc_cap(void);

src/northbridge/intel/sandybridge/raminit_mrc.c

@@ -340,7 +340,7 @@ static void disable_p2p(void)
 
 static void setup_sdram_meminfo(struct pei_data *pei_data);
 
-void perform_raminit(int s3resume)
+void perform_raminit(bool s3resume)
 {
 	const struct northbridge_intel_sandybridge_config *cfg = config_of_soc();
 	struct pei_data pei_data = {
@@ -412,7 +412,7 @@ void perform_raminit(int s3resume)
 		hexdump(mrc_var, sizeof(*mrc_var));
 	}
 
-	const int cbmem_was_initted = !cbmem_recovery(s3resume);
+	const bool cbmem_was_initted = !cbmem_recovery(s3resume);
 	if (!s3resume)
 		save_mrc_data(&pei_data);
 

src/northbridge/intel/sandybridge/raminit_native.c

@@ -630,7 +630,7 @@ static void dram_ioregs(ramctr_timing *ctrl)
 	printram("done\n");
 }
 
-int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size)
+int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, bool s3resume, int me_uma_size)
 {
 	int err;
 

src/northbridge/intel/sandybridge/romstage.c

@@ -16,7 +16,7 @@
 #include <southbridge/intel/common/pmclib.h>
 #include <elog.h>
 
-__weak void mainboard_early_init(int s3resume)
+__weak void mainboard_early_init(bool s3resume)
 {
 }
 
@@ -48,7 +48,7 @@ static void early_pch_reset_pmcon(void)
 /* The romstage entry point for this platform is not mainboard-specific, hence the name */
 void mainboard_romstage_entry(void)
 {
-	int s3resume = 0;
+	bool s3resume = false;
 
 	if (mchbar_read16(SSKPD_HI) == 0xcafe)
 		system_reset();

src/northbridge/intel/sandybridge/sandybridge.h

@@ -64,8 +64,8 @@ void northbridge_romstage_finalize(void);
 void early_init_dmi(void);
 
 /* mainboard_early_init: Optional callback, run after console init but before raminit. */
-void mainboard_early_init(int s3resume);
-void perform_raminit(int s3resume);
+void mainboard_early_init(bool s3resume);
+void perform_raminit(bool s3resume);
 void report_memory_config(void);
 enum platform_type get_platform_type(void);
 

src/northbridge/intel/x4x/raminit.c

@@ -561,7 +561,8 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
 {
 	struct sysinfo s, *ctrl_cached;
 	u8 reg8;
-	int fast_boot, cbmem_was_inited;
+	int fast_boot;
+	bool cbmem_was_inited;
 	size_t mrc_size;
 
 	timestamp_add_now(TS_INITRAM_START);
@@ -640,7 +641,7 @@ void sdram_initialize(int boot_path, const u8 *spd_map)
 
 	printk(BIOS_DEBUG, "RAM initialization finished.\n");
 
-	int s3resume = boot_path == BOOT_PATH_RESUME;
+	bool s3resume = boot_path == BOOT_PATH_RESUME;
 
 	cbmem_was_inited = !cbmem_recovery(s3resume);
 	if (!fast_boot)

src/northbridge/via/cx700/romstage.c

@@ -57,7 +57,7 @@ void mainboard_romstage_entry(void)
 
 	sdram_enable(&config->dram_cfg);
 
-	cbmem_recovery(/* s3resume => */0);
+	cbmem_recovery(/* s3resume => */false);
 
 	prepare_and_run_postcar();
 }

src/security/intel/txt/ramstage.c

@@ -173,7 +173,7 @@ static void init_intel_txt(void *unused)
 		log_ibb_measurements();
 	}
 
-	int s3resume = acpi_is_wakeup_s3();
+	bool s3resume = acpi_is_wakeup_s3();
 	if (!s3resume && !CONFIG(INTEL_CBNT_SUPPORT)) {
 		printk(BIOS_INFO, "TEE-TXT: Scheck...\n");
 		if (intel_txt_run_bios_acm(ACMINPUT_SCHECK) < 0) {

src/soc/amd/stoneyridge/romstage.c

@@ -55,7 +55,7 @@ void __noreturn romstage_main(void)
 	msr_t base, mask;
 	msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
 	int vmtrrs = mtrr_cap.lo & MTRR_CAP_VCNT;
-	int s3_resume = acpi_is_wakeup_s3();
+	bool s3_resume = acpi_is_wakeup_s3();
 	int i;
 
 	soc_enable_psp_early();

src/soc/intel/baytrail/romstage/raminit.c

@@ -129,7 +129,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
 	mp->prev_sleep_state = prev_sleep_state;
 	mp->rmt_enabled = CONFIG(MRC_RMT);
 
-	int s3resume = prev_sleep_state == ACPI_S3;
+	bool s3resume = prev_sleep_state == ACPI_S3;
 
 	/* Default to 2GiB IO hole. */
 	if (!mp->io_hole_mb)
@@ -182,7 +182,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
 
 	ret = mrc_entry(mp);
 
-	int cbmem_was_initted = !cbmem_recovery(s3resume);
+	bool cbmem_was_initted = !cbmem_recovery(s3resume);
 	if (s3resume && !cbmem_was_initted) {
 		/* Failed S3 resume, reset to come up cleanly */
 		printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n");

src/soc/intel/baytrail/romstage/romstage.c

@@ -108,7 +108,7 @@ void mainboard_romstage_entry(void)
 
 	printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state);
 
-	int s3resume = prev_sleep_state == ACPI_S3;
+	bool s3resume = prev_sleep_state == ACPI_S3;
 
 	elog_boot_notify(s3resume);
 

src/soc/intel/broadwell/include/soc/romstage.h

@@ -3,7 +3,7 @@
 #ifndef _BROADWELL_ROMSTAGE_H_
 #define _BROADWELL_ROMSTAGE_H_
 
-void mainboard_post_raminit(const int s3resume);
+void mainboard_post_raminit(const bool s3resume);
 
 struct chipset_power_state;
 struct chipset_power_state *fill_power_state(void);

src/soc/intel/broadwell/raminit.c

@@ -191,7 +191,7 @@ static int make_channel_disabled_mask(const struct spd_info *spdi, int ch)
 
 void perform_raminit(const struct chipset_power_state *const power_state)
 {
-	const int s3resume = power_state->prev_sleep_state == ACPI_S3;
+	const bool s3resume = power_state->prev_sleep_state == ACPI_S3;
 
 	struct pei_data pei_data = { 0 };
 
@@ -232,7 +232,7 @@ void perform_raminit(const struct chipset_power_state *const power_state)
 
 	timestamp_add_now(TS_INITRAM_END);
 
-	int cbmem_was_initted = !cbmem_recovery(s3resume);
+	bool cbmem_was_initted = !cbmem_recovery(s3resume);
 	if (s3resume && !cbmem_was_initted) {
 		/* Failed S3 resume, reset to come up cleanly */
 		printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n");

src/soc/intel/broadwell/romstage.c

@@ -12,7 +12,7 @@
 #include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include <stdint.h>
 
-__weak void mainboard_post_raminit(const int s3resume)
+__weak void mainboard_post_raminit(const bool s3resume)
 {
 }
 

src/southbridge/intel/lynxpoint/early_pch_native.c

@@ -83,7 +83,7 @@ static void early_sata_init(const uint8_t pch_revision)
 	pci_or_config8(PCH_SATA_DEV, SATA_PCS, sata_pcs);
 }
 
-void early_pch_init_native(int s3resume)
+void early_pch_init_native(bool s3resume)
 {
 	const uint8_t pch_revision = pci_read_config8(PCH_LPC_DEV, PCI_REVISION_ID);
 

src/southbridge/intel/lynxpoint/pch.h

@@ -116,7 +116,7 @@ void pch_dmi_setup_physical_layer(void);
 void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm);
 void early_usb_init(void);
 void early_thermal_init(void);
-void early_pch_init_native(int s3resume);
+void early_pch_init_native(bool s3resume);
 
 void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
 void usb_ehci_disable(pci_devfn_t dev);