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soc/intel/pantherlake: Add hysteresis window UPDs support

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This commit introduces configuration options for P-core and E-core
hysteresis time windows to support acoustic noise mitigation on Intel
Panther Lake (PTL) System on Chips (SoCs).

Change-Id: Ic3bceda06adf4e0a81b0503e5fb65895bfad2c12
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89333
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
This commit is contained in:
Jeremy Compostella 2025-09-24 14:11:57 -07:00 • committed by Jérémy Compostella
commit 0d1545ffac
2 changed files with 6 additions and 0 deletions
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4
src/soc/intel/pantherlake/chip.h
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@ -651,6 +651,10 @@ struct soc_intel_pantherlake_config {
* as per `enum slew_rate` data type.
*/
uint8_t slow_slew_rate_config[NUM_VR_DOMAINS];
/* P-cores Hysteresis time window ranges from 1 to 50 ms. */
uint8_t pcore_hysteresis_window_ms;
/* E-cores Hysteresis time window ranges from 1 to 50 ms. */
uint8_t ecore_hysteresis_window_ms;
uint16_t max_dram_speed_mts;

2
src/soc/intel/pantherlake/romstage/fsp_params.c
View file

@ -363,6 +363,8 @@ static void fill_fspm_acoustic_params(FSP_M_CONFIG *m_cfg,
return;
m_cfg->AcousticNoiseMitigation = config->enable_acoustic_noise_mitigation;
m_cfg->PcoreHysteresisWindow = config->pcore_hysteresis_window_ms;
m_cfg->EcoreHysteresisWindow = config->ecore_hysteresis_window_ms;
for (size_t i = 0; i < ARRAY_SIZE(config->disable_fast_pkgc_ramp); i++) {
m_cfg->FastPkgCRampDisable[i] = config->disable_fast_pkgc_ramp[i];