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soc/intel/pantherlake: Rely on FSP_DIMM_INFO

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This patch updates the Panther Lake SoC configuration to select the
`FSP_DIMM_INFO` Kconfig option. This change instructs the build system
to use the common FSP driver implementation for retrieving and storing
DIMM information.

As a result, the duplicated, SoC-specific DIMM information retrieval
logic is dropped from the Panther Lake SoC code base, centralizing
the memory parsing mechanism.

TEST=Able to build and boot google/kinmen. Verify the memory
related information is proper as part of the SMBIOS table.

Change-Id: I3323d3add9213cc384b9a2ca978681287d0e1822
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Subrata Banik 2025-10-09 17:06:20 +05:30
commit e168a516e4
2 changed files with 8 additions and 104 deletions
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1
src/soc/intel/pantherlake/Kconfig
View file

@ -19,6 +19,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
select DISPLAY_FSP_VERSION_INFO_2
select DRAM_SUPPORT_DDR5
select DRIVERS_USB_ACPI
select FSP_DIMM_INFO
select FAST_SPI_DMA
select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
select FSP_COMPRESS_FSP_S_LZ4

111
src/soc/intel/pantherlake/romstage/romstage.c
View file

@ -3,14 +3,12 @@
#include <arch/romstage.h>
#include <cbmem.h>
#include <console/console.h>
#include <fsp/util.h>
#include <fsp/api.h>
#include <intelblocks/cfg.h>
#include <intelblocks/cse.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/smbus.h>
#include <intelblocks/thermal.h>
#include <memory_info.h>
#include <soc/intel/common/smbios.h>
#include <soc/iomap.h>
#include <soc/pm.h>
#include <soc/romstage.h>
@ -18,107 +16,12 @@
#include <string.h>
#include <timestamp.h>
#define FSP_SMBIOS_MEMORY_INFO_GUID \
{ \
0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \
0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \
}
/* Save the DIMM information for SMBIOS table 17 */
static void save_dimm_info(void)
void platform_fill_dimm_info_args(const DIMM_INFO *src_dimm,
const MEMORY_INFO_DATA_HOB *meminfo_hob,
struct dimm_fill_args *args)
{
int node, channel, dimm, dimm_max, index;
size_t hob_size;
const CONTROLLER_INFO *ctrlr_info;
const CHANNEL_INFO *channel_info;
const DIMM_INFO *src_dimm;
struct dimm_info *dest_dimm;
struct memory_info *mem_info;
const MEMORY_INFO_DATA_HOB *meminfo_hob;
const uint8_t smbios_memory_info_guid[sizeof(EFI_GUID)] = FSP_SMBIOS_MEMORY_INFO_GUID;
const uint8_t *serial_num;
const char *dram_part_num = NULL;
size_t dram_part_num_len = 0;
/* Locate the memory info HOB, presence validated by raminit */
meminfo_hob = fsp_find_extension_hob_by_guid(
smbios_memory_info_guid,
&hob_size);
if (!meminfo_hob || hob_size == 0) {
printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n");
return;
}
/*
* Allocate CBMEM area for DIMM information used to populate SMBIOS
* table 17
*/
mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
if (!mem_info) {
printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n");
return;
}
memset(mem_info, 0, sizeof(*mem_info));
/* Allow mainboard to override DRAM part number. */
dram_part_num = mainboard_get_dram_part_num();
if (dram_part_num)
dram_part_num_len = strlen(dram_part_num);
/* Save available DIMM information */
index = 0;
dimm_max = ARRAY_SIZE(mem_info->dimm);
for (node = 0; node < MAX_NODE; node++) {
ctrlr_info = &meminfo_hob->Controller[node];
for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) {
channel_info = &ctrlr_info->ChannelInfo[channel];
if (channel_info->Status != CHANNEL_PRESENT)
continue;
for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) {
src_dimm = &channel_info->DimmInfo[dimm];
dest_dimm = &mem_info->dimm[index];
if (src_dimm->Status != DIMM_PRESENT)
continue;
/* If there is no DRAM part number overridden by
* mainboard then use original one. */
if (!dram_part_num) {
dram_part_num_len = sizeof(src_dimm->ModulePartNum);
dram_part_num = (const char *)
&src_dimm->ModulePartNum[0];
}
uint8_t memProfNum = meminfo_hob->MemoryProfile;
serial_num = src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL;
/* Populate the DIMM information */
dimm_info_fill(dest_dimm,
src_dimm->DimmCapacity,
meminfo_hob->MemoryType,
meminfo_hob->ConfiguredMemoryClockSpeed,
src_dimm->RankInDimm,
channel_info->ChannelId,
src_dimm->DimmId,
dram_part_num,
dram_part_num_len,
serial_num,
src_dimm->DataWidth,
meminfo_hob->VddVoltage[memProfNum],
meminfo_hob->EccSupport,
src_dimm->MfgId.Data,
src_dimm->SpdModuleType,
node,
meminfo_hob->MaximumMemoryClockSpeed);
index++;
}
}
}
mem_info->dimm_cnt = index;
if (mem_info->dimm_cnt == 0)
printk(BIOS_ERR, "No DIMMs found\n");
else
printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
args->data_width = src_dimm->DataWidth;
args->mfg_id_arg = src_dimm->MfgId.Data;
}
void mainboard_romstage_entry(void)
@ -155,5 +58,5 @@ void mainboard_romstage_entry(void)
fsp_memory_init(s3wake);
pmc_set_disb();
if (!s3wake)
save_dimm_info();
fsp_save_dimm_info();
}