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soc/intel/pantherlake: Remove unused TxDqDqs retraining parameter

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This commit removes the unused `lp_ddr_dq_dqs_re_training` field from
various memory configuration structures across multiple mainboard
variants, including google/fatcat, google/ocelot, and intel/ptlrvp.
This change should reduce complexity and prevent unnecessary memory
operations related to DQ/DQS retraining.

Write DqDqs retraining is enabled in Intel FSP by default. This can be
verified with debug FSP logs by checking WRTRETRAIN and
"MRC task -- Write DQ/DQS Retraining -- Started." prints.

BUG=None
TEST=Boot to OS on google fatcat board and verify DQ/DQS retraining.

Change-Id: Ib298b06260f576bee1f078dc09b1e23a9772b431
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89334
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Bora Guvendik 2025-09-24 14:23:33 -07:00 • committed by Jérémy Compostella
commit f61ffb68c9
11 changed files with 0 additions and 31 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/mainboard/google/fatcat/variants/fatcat/memory.c
View file

@ -55,8 +55,6 @@ static const struct mb_cfg lp5_mem_config = {
.ect = true, /* Early Command Training */
.lp_ddr_dq_dqs_re_training = 1,
.user_bd = BOARD_TYPE_ULT_ULX,
.lp5x_config = {

2
src/mainboard/google/fatcat/variants/felino/memory.c
View file

@ -55,8 +55,6 @@ static const struct mb_cfg lp5_mem_config = {
.ect = true, /* Early Command Training */
.lp_ddr_dq_dqs_re_training = 1,
.user_bd = BOARD_TYPE_ULT_ULX,
.lp5x_config = {

2
src/mainboard/google/fatcat/variants/francka/memory.c
View file

@ -55,8 +55,6 @@ static const struct mb_cfg lp5_mem_config = {
.ect = true, /* Early Command Training */
.lp_ddr_dq_dqs_re_training = 1,
.user_bd = BOARD_TYPE_ULT_ULX,
.lp5x_config = {

2
src/mainboard/google/fatcat/variants/kinmen/memory.c
View file

@ -55,8 +55,6 @@ static const struct mb_cfg lp5_mem_config = {
.ect = true, /* Early Command Training */
.lp_ddr_dq_dqs_re_training = 1,
.user_bd = BOARD_TYPE_ULT_ULX,
.lp5x_config = {

2
src/mainboard/google/fatcat/variants/lapis/memory.c
View file

@ -55,8 +55,6 @@ static const struct mb_cfg lp5_mem_config = {
.ect = true, /* Early Command Training */
.lp_ddr_dq_dqs_re_training = 1,
.user_bd = BOARD_TYPE_ULT_ULX,
.lp5x_config = {

2
src/mainboard/google/fatcat/variants/moonstone/memory.c
View file

@ -55,8 +55,6 @@ static const struct mb_cfg lp5_mem_config = {
.ect = true, /* Early Command Training */
.lp_ddr_dq_dqs_re_training = 1,
.user_bd = BOARD_TYPE_ULT_ULX,
.lp5x_config = {

2
src/mainboard/google/ocelot/variants/matsu/memory.c
View file

@ -35,8 +35,6 @@ static const struct mb_cfg lp5_mem_config = {
.ect = true, /* Early Command Training */
.lp_ddr_dq_dqs_re_training = 1,
.user_bd = BOARD_TYPE_ULT_ULX,
.lp5x_config = {

4
src/mainboard/google/ocelot/variants/ocelot/memory.c
View file

@ -39,8 +39,6 @@ static const struct mb_cfg lp5_mem_config = {
.ect = true, /* Early Command Training */
.lp_ddr_dq_dqs_re_training = 1,
.user_bd = BOARD_TYPE_ULT_ULX,
.lp5x_config = {
@ -55,8 +53,6 @@ static const struct mb_cfg ddr5_mem_config = {
.user_bd = BOARD_TYPE_ULT_ULX,
.lp_ddr_dq_dqs_re_training = 1,
.ddr_config = {
.dq_pins_interleaved = false,
},

2
src/mainboard/google/ocelot/variants/ojal/memory.c
View file

@ -38,8 +38,6 @@ static const struct mb_cfg lp5_mem_config = {
.ect = true, /* Early Command Training */
.lp_ddr_dq_dqs_re_training = 1,
.user_bd = BOARD_TYPE_ULT_ULX,
.lp5x_config = {

8
src/mainboard/intel/ptlrvp/variants/ptlrvp/memory.c
View file

@ -56,8 +56,6 @@ static const struct mb_cfg gcs_mem_config = {
.ect = true, /* Early Command Training */
.lp_ddr_dq_dqs_re_training = 1,
.user_bd = BOARD_TYPE_ULT_ULX,
.lp5x_config = {
@ -116,8 +114,6 @@ static const struct mb_cfg lp5_t3_mem_config = {
.ect = true, /* Early Command Training */
.lp_ddr_dq_dqs_re_training = 1,
.user_bd = BOARD_TYPE_ULT_ULX,
.lp5x_config = {
@ -176,8 +172,6 @@ static const struct mb_cfg lp5_t4_mem_config = {
.ect = true, /* Early Command Training */
.lp_ddr_dq_dqs_re_training = 1,
.user_bd = BOARD_TYPE_ULT_ULX,
.lp5x_config = {
@ -196,8 +190,6 @@ static const struct mb_cfg ddr5_mem_config = {
.user_bd = BOARD_TYPE_ULT_ULX,
.lp_ddr_dq_dqs_re_training = 1,
.ddr_config = {
.dq_pins_interleaved = false,
}

3
src/soc/intel/pantherlake/include/soc/meminit.h
View file

@ -102,9 +102,6 @@ struct mb_cfg {
/* Command Mirror */
uint8_t cmd_mirror;
/* Enable/Disable TxDqDqs Retraining for LP5 */
uint8_t lp_ddr_dq_dqs_re_training;
};
void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,