erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

soc/intel/pantherlake: Update thermal design current parameters

Browse source 
Update thermal design current (TDC) values for GT domain across
multiple PTL SKUs based on input from Power and Performance team.

BUG=none
TEST=Boot to OS on fatcat device and check performance.

Change-Id: I6333f8b5db8c7fc1739d0772d83bfe602a837a53
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89697
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Ma, Zhixing <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Bora Guvendik 2025-10-23 13:30:39 -07:00 • committed by Matt DeVillier
commit 105598545e
1 changed files with 4 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

9
src/soc/intel/pantherlake/chipset_ptl.cb
View file

@ -10,7 +10,7 @@ chip soc/intel/pantherlake
}"
register "thermal_design_current[PTL_SKU_1]" = "{
[VR_DOMAIN_IA] = 23 * 8,
[VR_DOMAIN_GT] = 15 * 8
[VR_DOMAIN_GT] = 23 * 8
}"
register "icc_max[PTL_SKU_1]" = "{
[VR_DOMAIN_IA] = 80 * 4,
@ -27,7 +27,7 @@ chip soc/intel/pantherlake
}"
register "thermal_design_current[PTL_SKU_5]" = "{
[VR_DOMAIN_IA] = 23 * 8,
[VR_DOMAIN_GT] = 15 * 8
[VR_DOMAIN_GT] = 23 * 8
}"
register "icc_max[PTL_SKU_5]" = "{
[VR_DOMAIN_IA] = 80 * 4,
@ -44,7 +44,7 @@ chip soc/intel/pantherlake
}"
register "thermal_design_current[PTL_SKU_2]" = "{
[VR_DOMAIN_IA] = 31 * 8,
[VR_DOMAIN_GT] = 25 * 8
[VR_DOMAIN_GT] = 44 * 8
}"
register "icc_max[PTL_SKU_2]" = "{
[VR_DOMAIN_IA] = 107 * 4,
@ -67,7 +67,7 @@ chip soc/intel/pantherlake
register "thermal_design_current[PTL_SKU_6]" = "{
[VR_DOMAIN_IA] = 31 * 8,
[VR_DOMAIN_GT] = 25 * 8
[VR_DOMAIN_GT] = 44 * 8
}"
register "icc_max[PTL_SKU_6]" = "{
[VR_DOMAIN_IA] = 90 * 4,
@ -77,7 +77,6 @@ chip soc/intel/pantherlake
}"
register "tdc_mode[VR_DOMAIN_IA]" = "TDC_IRMS"
register "tdc_mode[VR_DOMAIN_GT]" = "TDC_IRMS"
register "tdc_time_window_ms[VR_DOMAIN_IA]" = "28000"
# Set the power state thresholds according to document 813278