Add support to configure DFSR table, introduce qupv3_clock_v2
structure to calculate register addresses for serial engines 2
and 3. Update CBCR registers to use the new structure for QUPv3
clock enablement.
BUG=b:444617760
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Dump DFSR registers for corresponding QUP and check if values are
updated properly into correct register address.
Change-Id: Ibd7e4bf121bd99130336047a50ed70d4cbec2234
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90145
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Toggle the RTC BUC control bit for Top Swap bootblock selection based on
the "attempt_slot_b" flag CMOS option, allowing to select which of the
BOOTBLOCK or TOP_SWAP regions to boot from.
This means that after an update, the CMOS option can be set to boot from
the newer TOP_SWAP bootblock. In case of failure, CMOS can be cleared to
revert to the known-good base BOOTBLOCK.
This is part of ongoing implementation of a redundancy feature proposed
on the mailing list:
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
Switching between identical bootblocks doesn't impact further boot flow,
i.e. selecting which FMAP region to load consecutive stages from.
That is to be enabled in following patches.
So far tested and enabled for the Alder Lake SoC.
TEST=Boot VP6650, setting the attempt_slot_b flag to different values,
observing that it resets/continues booting correctly.
Change-Id: Ib183a1f72ee8585b2c4ad4376344de33ff54cbb9
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
To support Memory Tagging Extension (MTE), configure booker
(custom CI-700) registers related to MTE to set up MTE tag address.
According to CI-700 documentation, the por_mtu_tag_addr_base register is
only accessible by Secure accesses. Therefore these registers are now
configured in coreboot ramstage before passing to payloads.
BRANCH=rauru
BUG=b:438666196
TEST=manual test
Change-Id: I0d98cfee3e208a559116f84362528f005ea6f2c8
Signed-off-by: Jeff Xu <jeffxu@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90141
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
This commit updates the linker script to properly define and name the
DMA coherent memory regions used before and after DRAM initialization.
1. Rename Pre-RAM DMA Region:
The existing `DMA_COHERENT` region allocated in BSRAM at `0x14857000` is
renamed to `PRERAM_DMA_COHERENT`. This aligns the linker script with the
code changes (in `mmu.c`) which use the more specific name for the early
boot DMA buffer.
2. Add Post-RAM DMA Region:
A new region, `POSTRAM_DMA_COHERENT`, is defined at the very start of
DRAM (`0x80000000`) with an 8KB size. This region is intended for
general-purpose DMA operations that occur after DRAM is active,
ensuring a reserved, known, and uncached region for peripherals.
The memory map diagram comments are also updated to reflect these new
region names.
BUG=b:456953373
TEST=Able to build and boot google/quenbi.
Change-Id: I6fb4b9bf3425b311169ac43e1997f6574b571e00
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90098
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit relocates the following two regions:
1. `ddr_information`
2. `WATCHDOG_TOMBSTONE`
Previously, these regions were allocated in a higher address range
(starting near 0x14800000).
The regions are now defined within SSRAM`:
- `ddr_information` is moved from `0x14860000` to `0x146ABFE8`.
- `WATCHDOG_TOMBSTONE` is moved from `0x14818FFC` to `0x146ABFFC`.
This memory map change updates the linker script's visual diagram and
section definitions to reflect the new memory layout.
BUG=b:456953373
TEST=Able to build google/quenbi.
Change-Id: I4545722a836ec472e8086d1a941515cb3956c763
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90052
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MMU configuration in qc_mmu_dram_config_post_dram_init() needs to
include the memory region allocated for DMA coherent buffers.
Map the `postram_dma_coherent` region as UNCACHED_RAM to ensure memory
writes bypass the CPU cache hierarchy.
The mapping is only configured if the `_postram_dma_coherent` address
is different from `_preram_dma_coherent` address aka migration of the
region.
This is necessary for DMA operations that occur after DRAM is
initialized.
BUG=b:456953373
TEST=Able to build google/quenbi.
Change-Id: If5f625ad74f4f6ea244c8b377543be3666122cea
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch relocates the coreboot stack from the BSRAM (Boot IMEM)
region to the SSRAM (Shared System RAM) region.
The 16K stack definition is moved from:
BSRAM region (0x14850000)
To:
SSRAM region (0x14680000)
This move is crucial because the BSRAM region is actively cleared during
the later stages of the IP loading process, which would wipe the stack
and lead to instability. Placing the stack in the persistent SSRAM
ensures it remains accessible throughout the early boot process.
BUG=BUG=b:456953373
TEST=Able to build google/quenbi w/ new stack region.
Change-Id: I59cd14fed2a5907bcbb8bed027dd5a55eb73e56d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90137
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Instrument the Qualcomm QCLib flow with timestamps to measure
execution time for both the initial loading/running phase and the
subsequent re-entry phase.
The timestamps are placed as follows:
- TS_QUALCOMM_QCLIB_INIT_START/END: Tracks the execution of
`qclib_load_and_run()`.
- TS_QUALCOMM_QCLIB_REINIT_START/END: Tracks the execution of
`qclib_rerun()`, which typically handles the AOP bring-up.
This instrumentation helps in profiling and optimizing the boot
performance on Qualcomm platforms.
Change-Id: I200ea5a78f4630000e80aed6dc38581af4d2e8aa
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90112
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
AMD Renoir soc is very similar to Cezanne and has been used without
differentiation until now. Create the separation between SOCs using
Kconfig option to facilitate the customization of different features.
Also update SOC_AMD_RENOIR use on the crater mainboard.
Change-Id: I4783c4e3b17032b6d26ef67ddf954df3ce68fdf0
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87215
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit implements support for the FSP_VGA_MODE12_MONOCHROME
Kconfig option within the Panther Lake romstage code.
By checking for the CONFIG_FSP_VGA_MODE12_MONOCHROME option, we
set the corresponding VGA_INIT_CONTROL_MODE12_MONOCHROME bit in
the FSP_M_CONFIG structure.
This ensures that when a 1-bit-per-pixel framebuffer is used, the
Intel FSP is correctly informed to replicate the data across the
remaining color planes for display, saving 75% of framebuffer memory
in romstage.
Key changes:
- Define the new VGA_INIT_CONTROL_MODE12_MONOCHROME control bit.
- Conditionally set this control bit in setup_vga_mode12_params()
when CONFIG_FSP_VGA_MODE12_MONOCHROME is enabled.
BUG=b:406725440
TEST=Verify VGA text rotation on Google/Felino.
Change-Id: I1dec24bb7ed44ca07babe0aa6886a50952d3faa2
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add common PCR write functions to write values directly to PCR
registers. These functions complement the existing read and
write-OR functions and provide a complete PCR access interface
for ACPI code.
WPCR: Generic PCR write function in the ACPI library
PCRW: PCH-specific PCR write function that calls WPCR
BUG=none
TEST=Build test on platforms using PCR functions. Verify ACPI code can
successfully write to PCR registers using the new functions.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I2c74dffda94a3ab34bd71177a3878b8d4c3119cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com>
Add dual display pipe path. Also change the original single pipe path
with DSC engine configured in relay mode.
TEST=build pass and test display logo ok
BUG=b:424782827
Change-Id: I2373ea63a08bf25a7eef45b947d218b445b62130
Signed-off-by: Nancy Lin <nancy.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90039
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The firmware binaries for UART, SPI, I2C, and GSI are loaded early in
the boot process. Disable CBFS compression for these files by explicitly
setting $(CBFS_..._compression) to 'none'.
This ensures the firmware is stored and loaded as a raw binary,
mitigating potential boot time impact with decompression.
BUG=b:449871690
TEST=Able to save ~10ms of the boot time while booting google/quenbi.
Change-Id: I0418aadeb860143e766b0fe1ba10a0316d4cc6a7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90040
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor Kconfig dependency by moving the selection of Secure OS
(TrustZone/TEE) features from the mainboard configuration to the
specific SoC configuration layer.
The selections for `ARM64_USE_SECURE_OS` and
`ARM64_USE_SECURE_OS_PAYLOAD` are moved from `BOARD_GOOGLE_BLUEY_COMMON`
to `SOC_QUALCOMM_HAMOA`.
This ensures that the Secure OS requirements are correctly associated
with the Hamoa chipset family itself, leading to better modularity and
future compatibility for Hamoa-based platforms.
Crucially, this change allows for precise control of the Secure OS
(BL32 firmware) applicability. By selecting the feature only within
`SOC_QUALCOMM_HAMOA`, we can ensure that platforms utilizing the
"Purwa SoC" family (which currently does not have a ready/available
SecureOS) automatically avoid the selection of these Kconfig options.
The change is verified by ensuring the QTEE (SecureOS) feature is
disabled for platforms using the Purwa SoC, specifically verified on the
google/quenbi mainboard.
BUG=b:459268465
TEST=Ensure disabling QTEE aka SecureOS feature for google/quenbi w/
Purwa SoC.
AP firmware log shows the expected path taken when SecureOS is disabled:
```
WARNING: No QTEE entry point provided by BL2 boot loader,
Booting device without QTEE initialization.
```
Change-Id: Ic82a29a4330cc6e5f99727fc40ec73b38cbbc72d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90011
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for configuring the NVMe Power Loss Notification (PLN)
GPIO before powering on the NVMe device.
The Hamoa target has the PLN signal wired to SoC GPIO 157. The voltage
level conversion circuitry between the SoC (1.2V) and NVMe (3.3V) causes
the PLN signal voltage level to vary depending on the NVMe part used.
This change configures GPIO 157 as an input with no pull resistors and
2mA drive strength to ensure proper PLN signal handling and allow the
GPIO to be used for other hardware configurations.
Changes:
- Add NVME_PLN_GPIO definition for GPIO(157)
- Add nvme_core_pln_gpio() function to configure PLN GPIO
- Update gcom_pcie_power_on_ep() to call nvme_core_pln_gpio() before
enabling NVMe power regulator
TEST=Boot the Google/Bluey board and verify NVMe device is detected
and functional
Debug logs:
Initializing NVMe controller 1e0f:000c
nvme_ctrlr_init: PCI Command register = 0x2
nvme_ctrlr_init: PCI Status register = 0x10
nvme_ctrlr_init: PCI Command after bus master enable = 0x6
iosq_sz = 11, iocq_sz = 11
nvme_wait_status: Waiting for CSTS & 0x1 == 0x0, timeout=30000 ms
nvme_ctrlr_init: Waited 100ms after controller disable
nvme_enable_controller: CSTS before enable = 0x0
nvme_enable_controller: CAP register = 0x303c03ffff
nvme_enable_controller: CAP.TO timeout = 30000 ms
nvme_enable_controller: Writing CC register = 0x460001
nvme_enable_controller: CC register readback = 0x460001
nvme_wait_status: Waiting for CSTS & 0x1 == 0x1, timeout=30000 ms
nvme_enable_controller: CSTS after enable = 0x1 (status=0)
Identified NVMe model KBG50ZNS256G KIOXIA
Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0
Change-Id: Icc22cfd397a0adbc051b2b1a2178aeedb7389ac0
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90037
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Kconfig INTEL_TOP_SWAP_SEPARATE_REGIONS. When enabled, place the
regular bootblock in BOOTBLOCK and the Top Swap bootblock in TOPSWAP
to simplify A B updates. This lays groundwork for redundancy where one
bootblock remains a read only golden copy and the other is replaceable.
No swap control logic is added in this change. The option depends on
INTEL_ADD_TOP_SWAP_BOOTBLOCK and defaults to n so existing builds are
unchanged. A custom .fmd is required with BOOTBLOCK and TOPSWAP added
at the end of the image.
Background and update flow are described here:
Link: https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5Y
V35/
TEST=Build and run Protectli VP6650 (ADL-P), boots successfully with
correct microcode
Change-Id: I489406dd8d08ad85bb46324d3d009acb49b6c52a
Signed-off-by: Filip Lewiński <filip.lewinski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Introduce the `USB3_PORT_TX_CFG` macro to simplify the definition of
`usb3_port_config` structures.
This macro allows platform code to easily configure the Transmit
De-emphasis (`tx_de_emp`) value for a specific USB 3.0 port (identified
by `ocpin`).
This improves readability and reduces boilerplate when tuning signal
integrity settings for different USB ports on the board.
TEST=Able to build and boot google/kinmen.
Change-Id: I42565e2c573dfcff244a81bf7bcb9749eca52c05
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Convert SATA controller ACPI OperationRegion and Field definitions from
static ASL code to runtime-generated acpigen code. This allows the SATA
registers (STB5, SB5, and port fields P0ER-P3PR) to be conditionally
included in ACPI tables only when the SATA controller (device 00:11.0)
is enabled in the devicetree.
Including them unconditionally when the SATA PCI device is disabled
causes Windows to BSOD (ACPI BIOS ERROR), since the OpRegion references
a non-existent device.
Changes:
- Move SATA OperationRegion generation to sata.c using acpigen APIs
- Remove static SATA fields from acpi/pci_int.asl
- Add stoneyridge_sata_ops with acpi_fill_ssdt callback
- Update chipset_st.cb and chipset_cz.cb to use stoneyridge_sata_ops
- Remove Kconfig for SoC common SATA code, since no longer used
This reduces ACPI table size when SATA is disabled and properly scopes
SATA registers to the SATA device.
TEST=boot Win11 on google/liara without a BSOD
Change-Id: I6e7a9a60e3622368eac83c36efd384c8d92c2b05
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Add PCIe speed configuration for CPU root ports in FSP-M. Previously,
only PCH root port speed could be configured via FSP-S. Since CPU root
ports are initialized in FSP-M, they require configuration during
romstage.
This change uses the pcie_speed_control_to_upd() helper (now available
in the shared header) to convert devicetree PCIE_SPEED_control values
to FSP UPD indices. The configuration respects the pciexp_speed CMOS
option override if present, otherwise uses the devicetree setting.
TEST=Booted on mc_rpl1. Configured CPU RP to different PCIe speeds
(Gen1/Gen2/Gen3) via devicetree and verified correct link speed
negotiation with lspci for each configuration.
Change-Id: If3d871f238e7f063fef01c68cc371ae72ec9642c
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Include guards should cover the whole file.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Idbb7b26b31460ad5ac6b8a55a41eb274a8fcec92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com>
The console UART base address for Panther Lake is being updated from
0xfe036000 to 0xfe02c000 (as per FSP version 3272). This correction
ensures the console initializes with the correct UART base address.
TEST=Able to get FSP debug log while building google/fatcat.
Change-Id: Ic123189fb5689318a4940edcfcf206c32e3ccf26
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
This patch implements passing a "SerialIoUartDmaEnable" pointer to
FSP-S by parsing the devicetree.
Default (0) means PIO, while 1 means DMA.
Change-Id: Id0acfe0b30899a3019ea7e54067fc06cbc56bab6
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Extract PCIe RP clock configuration logic to a separate function,
following the same refactoring done for Meteor Lake in CB:89790.
Change-Id: I0abc48c066697199acfc7b77ee553e4e8c7b5119
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Extract the logic to configure PCIe RPs' clock source and clock request
signals to a separate function, so that the loop in `pcie_rp_init()` is
easier to reuse to program other PCIe-related settings.
While we're at it, make a few small improvements such as printing which
RP index is missing the clock structure definition as well as using the
`BIT()` macro (which is already used in `pcie_rp_init()`. Also retype a
few variables for the RP index, as it is never bigger than a `uint8_t`,
the type of the return value of the `get_max_pcie_port()` function.
Change-Id: I5583ef863630790cedd901e7bd30f4606f887a04
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
The USB port configuration macros (covering USB 2.0, 3.0, and TCSS) are
currently duplicated across multiple Intel SoC headers.
This patch refactors the definitions into a new, central IA common
header file. Moving these macros to a shared location eliminates
redundant code, simplifies maintenance, and ensures consistency across
platforms.
Specifically, this refactoring allows Intel Meteor Lake (MTL) and
Panther Lake (PTL) to immediately adopt the common definitions.
TEST=Able to build and boot google/kinmen.
Change-Id: I7fb1e4d100c6d72eba0e31f37aa58e6d741ceea6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89984
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Xeons implementation and the common intel implementation are identical
functionality wise so just use the common function.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I0ed42a93444e7cc0d339cf63cec4c4411b5b4f73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/86682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Retrieve SVID/SSID via devicetree and program to HDA device
BUG=b/458444964, b/454824561
TEST="lspci -s 00:1f.3 -x and check value in offset 0x2c-0x2f"
Change-Id: I6bf4b5f2cbce69429daabce83ab11c13272194f4
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89983
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
The code was indexing an array of clock sources using an RP index which
is not correct. As the intent of compliance mode seems to be to set all
clock sources to be free-running, do the same from a different place in
order to avoid potential out-of-bounds accesses.
To preserve original behaviour, exit early from `pcie_rp_init()`. While
this is rather crude, subsequent commits will refactor said function.
Change-Id: I89e6e9f85b7b86b0a74ece88641a378f2c0b599f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89788
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
`cfg[i].clk_req` is a `uint8_t` so use `%u` instead of `%d`.
Change-Id: I6c7a6ecbd2f5b917d44923d0ad6cb331d9bb054c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89789
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reduce maximum timeout from 100ms to 20ms for OTG Enablement polling
for USB Type-C.
Avoid OTG enablement polling when in sink mode
BUG=b:455551151
TEST: Verify USB3.0 (SS) works for C0/C1 on Google/Bluey.
Background:
During USB Type-C port initialization, the OTG (On-The-Go) status must
be verified when the port operates in source mode to ensure proper VBUS
power delivery. The previous implementation polled the OTG status
register with a 100ms timeout on all ports regardless of their role.
Previous Implementation Issues:
1. Overly conservative timeout: The 100ms maximum wait significantly
exceeded actual requirements, as OTG enablement consistently
completes in approximately 14ms under normal conditions
2. Inefficient polling logic: OTG status was polled even when ports
operated in sink mode, where OTG functionality is irrelevant since
the port receives rather than provides power
Improvements:
1. Timeout reduction: Decreased maximum polling duration from 100ms to
20ms, maintaining adequate margin (>40% headroom) while reducing boot
time by up to 80ms per sink-mode port
2. Mode-aware polling: Added logic to detect port role and skip OTG
status polling entirely for sink-mode ports, as demonstrated by the
"Primary in SNK mode - skipping OTG status read" log entry
The changes maintain full USB3.0 SuperSpeed functionality while
improving initialization efficiency. The 20ms timeout remains
sufficiently conservative to accommodate normal timing variations.
Debug logs:
[DEBUG] QMP PHY SS0 initialized and locked in 1671us,
phy_status: 0x86868686
[INFO ] Enabling Primary VBUS SuperSpeed
[INFO ] Primary in SNK mode - skipping OTG status read
[INFO ] Primary Type-C Status:
[INFO ] Misc Status (0x2B0B): 0x1a
[INFO ] Src Status (0x2B08): 0x00
[INFO ] Mode Config (0x2B44): 0x00
[INFO ] Interrupt En Cfg 1 (0x2B5E): 0xff
[INFO ] State Machine Status (0x2B09): 0x02
[DEBUG] USB HS PHY initialized for index 3
[DEBUG] QMP-1x16 USB4 DP PHY SS1 init
[DEBUG] QMP PHY SS1 initialized and locked in 1671us,
phy_status: 0x86868686
[INFO ] Enabling Secondary VBUS SuperSpeed
[INFO ] Secondary in SRC mode - OTG Status: 0x02, State: 0x02
(OTG Enabled) - Time: 14 ms
[INFO ] Secondary Type-C Status:
[INFO ] Misc Status (0x2B0B): 0x4b
[INFO ] Src Status (0x2B08): 0x08
[INFO ] Mode Config (0x2B44): 0x00
[INFO ] Interrupt En Cfg 1 (0x2B5E): 0xff
[INFO ] State Machine Status (0x2B09): 0xa6
confirmed that there are no otg polling for sink mode and
polling timeout is reduced to max of 20ms.
Change-Id: I7467248185c9d0526816ac62e1e1a1496440fddc
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit implements the configuration of VGA mode 12 in the
Intel Pantherlake SoC's romstage. It integrates the newly added
text rendering API to display user messages using a planar buffer
instead of the standard VGA message string.
The changes include:
- A call to `render_text_to_bitmap_buffer()` to draw the message
on the bitmap buffer.
- Determining the display orientation from the common SoC
configuration, with an override for a closed lid.
- Calculating and setting the correct position of the rendered
text in the VGA buffer.
- Duplicating the single-plane bitmap data to all required planes
for VGA mode 12.
- Setting the `VGA_INIT_CONTROL_MODE12` bit in the FSP-M UPD
to inform FSP to use the new mode.
- Implementing the `soc_set_vga_mode12_buffer()` API to set the
corresponding FSP-M UPD for VGA mode12 buffer address.
BUG=b:406725440
TEST=Verify VGA text rotation on Google/Felino.
Change-Id: Ic69fff0479020a31c7e6f0c52b4bdb25b1483bb9
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Enable hardware-managed microphone privacy by setting the
PchHdaMicPrivacyMode FSP UPD to 1. This feature was enabled by
default in FSP previously but has since changed to disabled by
default, so now coreboot explicitly enables this as it is a desired
feature for Chrome platforms.
The hardware-managed microphone privacy feature allows the platform
to control the microphone mute state at the hardware level for
enhanced privacy.
TEST=Verify UPD value is set correctly and HW managed mic privacy is
working as expected.
Change-Id: I9a20bd129103aae35550104f6a7025484ef5e9c1
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88451
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <srinivas.kulkarni@intel.com>
This commit removes the explicit CONFIG_HAVE_BMP_LOGO_COMPRESS_LZMA
definition from the Panther Lake Kconfig.
This local Kconfig setting, previously defaulted to 'n', is redundant
because the Panther Lake build now correctly inherits the intended
system-wide default, which is to use LZMA compression for the BMP
splash screen.
Removing this unnecessary Kconfig option simplifies the configuration
and results in a measured ~3ms reduction in boot time during the
firmware splash screen rendering phase on Panther Lake platforms.
w/o this patch:
```
963:returning from FspMultiPhaseSiInit 1,096,797 (102,937)
17:starting LZ4 decompress (ignore for x86) 1,111,606 (14,808)
18:finished LZ4 decompress (ignore for x86) 1,111,641 (34)
17:starting LZ4 decompress (ignore for x86) 1,119,857 (8,216)
18:finished LZ4 decompress (ignore for x86) 1,119,879 (21)
```
w/ this patch
```
963:returning from FspMultiPhaseSiInit 1,097,817 (103,211)
15:starting LZMA decompress (ignore for x86) 1,110,058 (12,241)
16:finished LZMA decompress (ignore for x86) 1,111,096 (1,037)
15:starting LZMA decompress (ignore for x86) 1,117,554 (6,458)
16:finished LZMA decompress (ignore for x86) 1,117,906 (352)
```
Change-Id: I64579e53c7f307d1430767da04a413f80016487f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
The pcie_speed_control_to_upd() helper function was only available in
aspm.c for PCH root port configuration. However, CPU root ports in
romstage also need to convert PCIE_SPEED_control enum values to FSP
UPD indices.
Move pcie_speed_control_to_upd() from aspm.c to pcie_helpers.c to
make it available in both romstage and ramstage. This allows both
PCH and CPU root port code to use the same conversion logic without
code duplication.
The helper handles the mapping between devicetree enum values and FSP
UPD values using the UPD_INDEX() macro (which subtracts 1):
- SPEED_DEFAULT (0) -> SPEED_AUTO (1) -> UPD_INDEX = 0
- SPEED_AUTO (1) -> UPD_INDEX = 0
- SPEED_GEN1 (2) -> UPD_INDEX = 1
- SPEED_GEN2 (3) -> UPD_INDEX = 2
- SPEED_GEN3 (4) -> UPD_INDEX = 3
- SPEED_GEN4 (5) -> UPD_INDEX = 4
This accounts for the fact that FSP expects 0-based indexing where
0 = Auto, 1 = Gen1, 2 = Gen2, etc.
TEST=Configured PCIE_SPEED_GEN2 for root port on mc_rpl1, booted and
verified with lspci -vv that device is limited to Gen2 speed
Change-Id: I0f70ad4da6f9f9e73b1c05648f0b206d5d61e07d
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Update thermal design current (TDC) values for GT domain across
multiple PTL SKUs based on input from Power and Performance team.
BUG=none
TEST=Boot to OS on fatcat device and check performance.
Change-Id: I6333f8b5db8c7fc1739d0772d83bfe602a837a53
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89697
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Ma, Zhixing <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure MMU for framebuffer region only when framebuffer region
exists (i.e., REGION_SIZE(framebuffer) > 0). Otherwise, the MMU would
raise assertion.
[INFO ] Mapping address range [0x0000040000000:0x0000240000000) as cacheable | read-write | non-secure | normal
[INFO ] Mapping address range [0x0000040000000:0x0000040100000) as non-cacheable | read-write | non-secure | normal
[DEBUG] Backing address range [0x0000040000000:0x0000080000000) with new L2 table @0x020da000
[DEBUG] Backing address range [0x0000040000000:0x0000040200000) with new L3 table @0x020db000
[INFO ] Mapping address range [0x0000000000000:0x0000000000000) as non-cacheable | read-write | non-secure | normal
[EMERG] ASSERTION ERROR: file 'src/arch/arm64/armv8/mmu.c', line 194
BUG=b:454457496
TEST=The assertion does not occur.
Change-Id: I8ab17bd289cd41a4568fddff2e556e5e49b1e6a4
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Add config `MEDIATEK_DSI_CPHY` to enable the MIPI C-PHY interface on
mt8189, including necessary register definitions and integrating with
the common MIPI driver, dsi_register_v2.
BUG=b:433422905,b:428854543
TEST=Check display initialization log on padme
mtk_display_init: 'TM TL121BVMS07' 1600x2560@60Hz
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Iac6c1b6d47331b63e7b45157bd60da93f104b0ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89620
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Introduce C-PHY support by adding PANEL_FLAG_CPHY flag, updating data
rate calculations, timing configurations, and register settings for
C-PHY operation.
To improve code reusability, the D-PHY and C-PHY specific
implementations are moved to `mtk_mipi_dphy.c` and `mtk_mipi_cphy.c`,
respectively.
BUG=b:433422905,b:428854543
BRANCH=skywalker
TEST=check log on padme
mtk_display_init: 'TM TL121BVMS07' 1600x2560@60Hz
Change-Id: I9e81551484e605e1d74b9983fe00b5d0eba69358
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
(cherry picked from commit 22a499836eeb6904e114023da6222b29da10f62f)
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89567
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Change the I2C connection speed type from uint32_t to the i2c_speed
enum type for better type safety and code consistency. While the
i2c_speed enum values correspond to actual speed values in Hz, using the
enum provides clearer intent and prevents invalid speed values.
Additionally, add logic to use standard I2C speed (100 kHz) when no
recommended or required speed is specified in the device tree, SoC
configuration, or device settings.
BUG=none
TEST=Boot Fatcat board to OS and verify correct I2C speed assignments in
'DSPD' Name object under THC device from SSDT. Confirm touch devices
operate at expected speeds.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ie01693544bebf9f748d16606fc13f39fe4069b03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89649
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add usb_repeater_spmi_init() and usb_repeater_spmi_tune() functions
for USB repeater internal to SMB2360 via SPMI configuration
during HS PHY initialization.
The usb_repeater_spmi_init() function enables Embedded USB2 control for
both SMB1 and SMB2 cores, while usb_repeater_spmi_tune() configures
optimal signal integrity parameters (IUSB2, USB2_SLEW, USB2_PREEM)
for reliable Type-C connectivity.
BUG=b:451814646
TEST=Verify USB2.0 (HS) works for C1 on Google/Bluey.
Without this CL -
USB2 key doesn't work for C1.
Verified HS1 functionality by turning on L14B from coreboot.
Before USB insertion:
firmware-shell: md 0x0a800420 8
0a800420: 000002a0 00000000 00000000 00000000 ................
0a800430: 000002a0 00000000 00000000 00000000 ................
firmware-shell: Added USB disk 2.
firmware-shell: md 0x0a800420 8
0a800420: 00000e03 00000000 00000000 00000000 ................
0a800430: 000002a0 00000000 00000000 00000000 ................
firmware-shell: Removed USB disk 2.
firmware-shell: md 0x0a800420 8
0a800420: 000002a0 00000000 00000000 00000000 ................
0a800430: 000002a0 00000000 00000000 00000000 ................
Change-Id: I24e0af062fc7a6b5effd9317ec5c0b2d89fe288e
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89613
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
To modify the Top Swap Block Size in the FD (if provided and
CONFIG_HAVE_IFD_BIN=y), set the following Kconfig variables:
- CONFIG_INTEL_HAS_TOP_SWAP
- CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK
- CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE
- CONFIG_INTEL_IFD_SET_TOP_SWAP_BOOTBLOCK_SIZE
Needed for the bootblock redundancy feature suggested at
https://mail.coreboot.org/archives/list/coreboot@coreboot.org/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
TEST=build VP66xx with custom Kconfig, check if TSBS is modified in FD
Change-Id: I94d3d3e2511a7e56392a9e34f845ae91602ce7f1
Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89493
Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename `common/dsi.c` to `common/dsi_common.c` since this file is used
by all SoCs. Rename `common/mtk_dsi_common.c` to `common/dsi_v1.c`, as
this file serves as the v1 implementation for all SoCs except mt8173.
These changes help clarify file usage and improve code readability.
BUG=b:433422905,b:428854543
BRANCH=skywaler
TEST=build passed
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: Ie711175434febce149a22742d78132842a6ec329
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89655
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
The touch controller's I2C bus speed configuration was previously set
directly through register values. This update introduces the use of the
I2C speed enum type to specify the desired connection speed, improving
clarity and reducing the risk of errors. A mapping function has been
added to convert the I2C speed enum into the appropriate register
value, factoring in the SoC's specific divider configuration. This
change ensures that the speed assignment aligns with the expected
operational parameters of the Panther Lake SoC touch controller.
BUG=none
TEST=Boot Fatcat board to OS and verify that the I2C speed assignments
are correct for the register value in SSDT.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I32e71ddcab77af2119c012bd3276f83c1bcea954
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Move mtk_dsi_reset() from mtk_mipi_dphy.c to mtk_dsi_common.c so that it
can also be used when using the C-PHY interface, improving code reuse.
BUG=b:433422905,b:428854543
BRANCH=skywaler
TEST=build passed
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I3f080127af4411584f66e307f7d2b13abbb051bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89619
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
