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soc/qualcomm/x1p42100: Update PCIE PHY init sequence

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Update PCIE PHY sequence as per hardware setting reference(HSR)
specifically, PCIE RC Config sequence(PCIE RC Cfg Seq).

Key changes:

- Add RX1-specific overrides applied after common RX settings
- Update TX lane mode register (LANE_MODE_3: 0x90 -> 0x51)
- Modify RX calibration and equalization parameters
- Adjust RX signal detection level (0xAA -> 0xCC)
- Add NVME_PLN_GPIO definition for Power Loss Notification

The changes ensure proper PHY initialization for PCIe Gen 4 link
establishment and improve signal integrity.

TEST=Boot the Google/Bluey board and check that the link is up

Debug logs:

[INFO ]  Enumerating buses...
[SPEW ]  Show all devs... Before device enumeration.
[SPEW ]  Root Device: enabled 1
[SPEW ]  CPU_CLUSTER: 0: enabled 1
[SPEW ]  DOMAIN: 00000000: enabled 1
[SPEW ]  PCI: 00:00:00.0: enabled 1
[SPEW ]  Compare with tree...
[SPEW ]  Root Device: enabled 1
[SPEW ]   CPU_CLUSTER: 0: enabled 1
[SPEW ]   DOMAIN: 00000000: enabled 1
[SPEW ]    PCI: 00:00:00.0: enabled 1
[DEBUG]  Root Device scanning...
[SPEW ]  scan_static_bus for Root Device
[DEBUG]  CPU_CLUSTER: 0 enabled
[INFO ]  Setup PCIe in RC mode
[DEBUG]  Skipping pipe
[DEBUG]  PCIe QPHY Initialized took 13us
[INFO ]  PCIe Link speed configured in Gen 4
[INFO ]  PCIe link is up
[NOTE ]  PCIe enumerated succussfully..
[DEBUG]  DOMAIN: 00000000 enabled
[DEBUG]  DOMAIN: 00000000 scanning...
[DEBUG]  PCI: pci_scan_bus for segment group 00 bus 00
[DEBUG]  PCI: 00:00:00.0 subordinate bus PCI Express
[DEBUG]  PCI: 00:00:00.0 [17cb/0111] enabled
[DEBUG]  PCI: 00:00:00.0 scanning...
[SPEW ]  do_pci_scan_bridge for PCI: 00:00:00.0
[DEBUG]  PCI: pci_scan_bus for segment group 00 bus 01
[DEBUG]  PCI: 00:01:00.0 [1e0f/000c] enabled
[INFO ]  PCI: 00:00:00.0: Setting Max_Payload_Size to 256
		for devices under this root port
[DEBUG]  scan_bus: bus PCI: 00:00:00.0 finished in 29 msecs
[DEBUG]  scan_bus: bus DOMAIN: 00000000 finished in 60 msecs
[SPEW ]  scan_static_bus for Root Device done
[DEBUG]  scan_bus: bus Root Device finished in 220 msecs
[INFO ]  done

Debug logs show successful PCIe enumeration with Gen 4 link up
and device [1e0f/000c] detected.

Change-Id: Ifb07839818e30622e35b6ee39af824fd5f19dec5
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Hari L 2025-11-14 11:39:32 +05:30 • committed by Matt DeVillier
commit 2b7b89ae31
2 changed files with 17 additions and 8 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/soc/qualcomm/common/pcie_common.c
View file

@ -379,6 +379,8 @@ static void configure_phy_port(pcie_qmp_phy_base_t *port, pcie_qmp_phy_cfg_t *qp
qcom_qmp_phy_config_lane(port->rx0, qphy->rx_tbl, qphy->rx_tbl_num, lane_base);
qcom_qmp_phy_config_lane(port->tx1, qphy->tx_tbl, qphy->tx_tbl_num, lane_base + 1);
qcom_qmp_phy_config_lane(port->rx1, qphy->rx_tbl, qphy->rx_tbl_num, lane_base + 1);
/* Apply RX1-specific overrides after common RX settings */
qcom_qmp_phy_config_lane(port->rx1, qphy->rx_tbl_sec, qphy->rx_tbl_num_sec, lane_base + 1);
qcom_qmp_phy_configure(port->ln_shrd, qphy->ln_shrd_tbl, qphy->ln_shrd_tbl_num);
qcom_qmp_phy_configure(port->serdes, qphy->serdes_tbl, qphy->serdes_tbl_num);
qcom_qmp_phy_configure(port->pcs, qphy->pcs_tbl, qphy->pcs_tbl_num);

23
src/soc/qualcomm/x1p42100/pcie.c
View file

@ -64,7 +64,7 @@ static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_pcie_tx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x03),
QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x01),
QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x10),
QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_3, 0x90),
QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_3, 0x51),
QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x34),
};
@ -72,12 +72,11 @@ static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_pcie_rx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN_RATE2, 0x0C),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN_RATE2, 0x04),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN_RATE3, 0x0A),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN_RATE3, 0x05),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x16),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IVCM_CAL_CTRL2, 0x82),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IVCM_CAL_CTRL2, 0x80),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IVCM_POSTCAL_OFFSET, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BKUP_CTRL1, 0x12),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BKUP_CTRL1, 0x15),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_1, 0x01),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_2, 0x01),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_3, 0x45),
@ -87,13 +86,13 @@ static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_pcie_rx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0B),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1C),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_PHPRE_CTRL, 0x20),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x01),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x3A),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x39),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE2_B0, 0x14),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE2_B1, 0xB3),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE2_B2, 0x58),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE2_B3, 0x9A),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE2_B4, 0x28),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE2_B4, 0x26),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE2_B5, 0xB6),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE2_B6, 0xEE),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_RATE3_B0, 0xE4),
@ -106,6 +105,12 @@ static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_pcie_rx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_RX_TX_ADPT_CTRL, 0x10),
};
/* RX1-specific overrides (applied after rx_tbl to RX1 lanes only) */
static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_pcie_rx_tbl_sec[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_MAN_VAL, 0x0B),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
};
static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_pcie_ln_shrd_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),
QMP_PHY_INIT_CFG(QSERDES_V4_LN_SHRD_DFE_DAC_ENABLE1, 0x88),
@ -132,7 +137,7 @@ static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_pcie_ln_shrd_tbl[] = {
static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_pcie_pcs_com_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_COM_G3S2_PRE_GAIN, 0x2E),
QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_COM_RX_SIGDET_LVL, 0xAA),
QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_COM_RX_SIGDET_LVL, 0xCC),
QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_COM_EQ_CONFIG4, 0x00),
QMP_PHY_INIT_CFG(QPHY_PCIE4_PCS_COM_EQ_CONFIG5, 0x22),
};
@ -231,6 +236,8 @@ static pcie_qmp_phy_cfg_t pcie6a_qmp_phy_1x4 = {
.tx_tbl_num = ARRAY_SIZE(x1p42100_qmp_pcie_tx_tbl),
.rx_tbl = x1p42100_qmp_pcie_rx_tbl,
.rx_tbl_num = ARRAY_SIZE(x1p42100_qmp_pcie_rx_tbl),
.rx_tbl_sec = x1p42100_qmp_pcie_rx_tbl_sec,
.rx_tbl_num_sec = ARRAY_SIZE(x1p42100_qmp_pcie_rx_tbl_sec),
.pcs_tbl = x1p42100_qmp_pcie_pcs_com_tbl,
.pcs_tbl_num = ARRAY_SIZE(x1p42100_qmp_pcie_pcs_com_tbl),
.pcs_misc_tbl = x1p42100_qmp_pcie_pcs_pcie_tbl,