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soc/qualcomm: Map the post-RAM DMA coherent buffer

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The MMU configuration in qc_mmu_dram_config_post_dram_init() needs to
include the memory region allocated for DMA coherent buffers.

Map the `postram_dma_coherent` region as UNCACHED_RAM to ensure memory
writes bypass the CPU cache hierarchy.

The mapping is only configured if the `_postram_dma_coherent` address
is different from `_preram_dma_coherent` address aka migration of the
region.

This is necessary for DMA operations that occur after DRAM is
initialized.

BUG=b:456953373
TEST=Able to build google/quenbi.

Change-Id: If5f625ad74f4f6ea244c8b377543be3666122cea
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Subrata Banik 2025-11-18 16:49:37 +00:00 • committed by Matt DeVillier
commit 958099b114
1 changed files with 3 additions and 0 deletions
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3
src/soc/qualcomm/common/mmu.c
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@ -73,4 +73,7 @@ void qc_mmu_dram_config_post_dram_init(size_t ddr_size)
CACHED_RAM);
mmu_config_range((void *)_aop_data_ram, REGION_SIZE(aop_data_ram),
CACHED_RAM);
if (_preram_dma_coherent != _postram_dma_coherent)
mmu_config_range((void *)_postram_dma_coherent, REGION_SIZE(postram_dma_coherent),
UNCACHED_RAM);
}