1fa24898e2
The pcie_speed_control_to_upd() helper function was only available in aspm.c for PCH root port configuration. However, CPU root ports in romstage also need to convert PCIE_SPEED_control enum values to FSP UPD indices. Move pcie_speed_control_to_upd() from aspm.c to pcie_helpers.c to make it available in both romstage and ramstage. This allows both PCH and CPU root port code to use the same conversion logic without code duplication. The helper handles the mapping between devicetree enum values and FSP UPD values using the UPD_INDEX() macro (which subtracts 1): - SPEED_DEFAULT (0) -> SPEED_AUTO (1) -> UPD_INDEX = 0 - SPEED_AUTO (1) -> UPD_INDEX = 0 - SPEED_GEN1 (2) -> UPD_INDEX = 1 - SPEED_GEN2 (3) -> UPD_INDEX = 2 - SPEED_GEN3 (4) -> UPD_INDEX = 3 - SPEED_GEN4 (5) -> UPD_INDEX = 4 This accounts for the fact that FSP expects 0-based indexing where 0 = Auto, 1 = Gen1, 2 = Gen2, etc. TEST=Configured PCIE_SPEED_GEN2 for root port on mc_rpl1, booted and verified with lspci -vv that device is limited to Gen2 speed Change-Id: I0f70ad4da6f9f9e73b1c05648f0b206d5d61e07d Signed-off-by: Kilian Krause <kilian.krause@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> |
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