soc/amd/turin_poc: Add Turin SoC structure as a copy of genoa_poc
Copied genoa_poc directory with Genoa occurrences renamed to Turin, case sensitive. Change-Id: I860f35a8b08dae1b3b18c65c96b0136f7b95913c Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88707 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This commit is contained in:
Michał Żygowski
Matt DeVillier
parent
668d643e5c
commit
3ef1cf9f84
41 changed files with 3218 additions and 0 deletions
211
src/soc/amd/turin_poc/Kconfig
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211
src/soc/amd/turin_poc/Kconfig
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@ -0,0 +1,211 @@
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## SPDX-License-Identifier: GPL-2.0-only
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config SOC_AMD_TURIN_POC
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bool
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if SOC_AMD_TURIN_POC
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config SOC_SPECIFIC_OPTIONS
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def_bool y
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select ACPI_SOC_NVS
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select ARCH_X86
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select DEFAULT_X2APIC
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select HAVE_ACPI_TABLES
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select HAVE_X86_64_SUPPORT
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select HAVE_SMI_HANDLER
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select SOC_AMD_COMMON
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select SOC_AMD_COMMON_BLOCK_ACPI
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select SOC_AMD_COMMON_BLOCK_ACPIMMIO
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select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE
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select SOC_AMD_COMMON_BLOCK_ACPI_IVRS
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select SOC_AMD_COMMON_BLOCK_ACPI_MADT
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select SOC_AMD_COMMON_BLOCK_AOAC
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select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
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select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
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select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
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select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN
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select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_MULTI_PCI_SEGMENT
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select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_EXTENDED_MMIO
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select SOC_AMD_COMMON_BLOCK_HAS_ESPI
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select SOC_AMD_COMMON_BLOCK_I2C
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select SOC_AMD_COMMON_BLOCK_I3C
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select SOC_AMD_COMMON_BLOCK_IOMMU
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select SOC_AMD_COMMON_BLOCK_LPC
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select SOC_AMD_COMMON_BLOCK_MCAX
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select SOC_AMD_COMMON_BLOCK_NONCAR
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select SOC_AMD_COMMON_BLOCK_PCI
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select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
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select SOC_AMD_COMMON_BLOCK_PSP_GEN2
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select SOC_AMD_COMMON_BLOCK_PSP_SPL
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select SOC_AMD_COMMON_BLOCK_SMI
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select SOC_AMD_COMMON_BLOCK_SMM
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select SOC_AMD_COMMON_BLOCK_SMU
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select SOC_AMD_COMMON_BLOCK_SMU_SX_ENTRY
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select SOC_AMD_COMMON_BLOCK_SPI
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select SOC_AMD_COMMON_BLOCK_SVI3
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select SOC_AMD_COMMON_BLOCK_TSC
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select SOC_AMD_COMMON_BLOCK_UART
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select SOC_AMD_COMMON_BLOCK_UCODE
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select SOC_AMD_COMMON_BLOCK_USE_ESPI
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select SOC_AMD_OPENSIL
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select OPENSIL_DRIVER
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config USE_X86_64_SUPPORT
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default y
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config CHIPSET_DEVICETREE
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string
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default "soc/amd/turin_poc/chipset.cb"
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config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
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int
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default 150
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config EARLY_RESERVED_DRAM_BASE
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hex
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default 0x7000000
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help
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This variable defines the base address of the DRAM which is reserved
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for usage by coreboot in early stages (i.e. before ramstage is up).
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This memory gets reserved in BIOS tables to ensure that the OS does
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not use it, thus preventing corruption of OS memory in case of S3
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resume.
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config EARLYRAM_BSP_STACK_SIZE
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hex
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default 0x1000
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config MAX_CPUS
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int
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default 384
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config PSP_APOB_DRAM_ADDRESS
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hex
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default 0x7001000
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help
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Location in DRAM where the PSP will copy the AGESA PSP Output
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Block.
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config PSP_APOB_DRAM_SIZE
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hex
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default 0x20000
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config PRERAM_CBMEM_CONSOLE_SIZE
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hex
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default 0x1600
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help
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Increase this value if preram cbmem console is getting truncated
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config C_ENV_BOOTBLOCK_SIZE
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hex
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default 0x20000
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help
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Sets the size of the bootblock stage that should be loaded in DRAM.
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This variable controls the DRAM allocation size in linker script
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for bootblock stage.
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config ROMSTAGE_ADDR
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hex
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default 0x7050000
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help
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Sets the address in DRAM where romstage should be loaded.
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config ROMSTAGE_SIZE
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hex
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default 0x70000
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help
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Sets the size of DRAM allocation for romstage in linker script.
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config ECAM_MMCONF_BASE_ADDRESS
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hex
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default 0xE0000000
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config ECAM_MMCONF_BUS_NUMBER
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int
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default 256
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menu "PSP Configuration Options"
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config AMDFW_CONFIG_FILE
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string
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default "src/soc/amd/turin_poc/fw.cfg"
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config PSP_DISABLE_POSTCODES
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bool "Disable PSP post codes"
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help
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Disables the output of port80 post codes from PSP.
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config PSP_INIT_ESPI
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bool "Initialize eSPI in PSP Stage 2 Boot Loader"
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help
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Select to initialize the eSPI controller in the PSP Stage 2 Boot
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Loader.
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config PSP_UNLOCK_SECURE_DEBUG
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bool
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default y
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config HAVE_PSP_WHITELIST_FILE
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bool "Include a debug whitelist file in PSP build"
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default n
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help
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Support secured unlock prior to reset using a whitelisted
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serial number. This feature requires a signed whitelist image
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and bootloader from AMD.
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If unsure, answer 'n'
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config PSP_WHITELIST_FILE
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string "Debug whitelist file path"
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depends on HAVE_PSP_WHITELIST_FILE
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config PSP_SOFTFUSE_BITS
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string "PSP Soft Fuse bits to enable"
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default ""
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help
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Space separated list of Soft Fuse bits to enable.
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Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG)
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Bit 7: Disable PSP postcodes on Renoir and newer chips only
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(Set by PSP_DISABLE_PORT80)
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Bit 15: PSP debug output destination:
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0=SoC MMIO UART, 1=IO port 0x3F8
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See #57299 (NDA) for additional bit definitions.
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endmenu
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config CONSOLE_UART_BASE_ADDRESS
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depends on CONSOLE_SERIAL && AMD_SOC_CONSOLE_UART
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hex
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default 0xfedc9000 if UART_FOR_CONSOLE = 0
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default 0xfedca000 if UART_FOR_CONSOLE = 1
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default 0xfedce000 if UART_FOR_CONSOLE = 2
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config SMM_TSEG_SIZE
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hex
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default 0x800000
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config ACPI_SSDT_PSD_INDEPENDENT
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bool "Allow core p-state independent transitions"
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default y
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help
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AMD recommends the ACPI _PSD object to be configured to cause
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cores to transition between p-states independently. A vendor may
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choose to generate _PSD object to allow cores to transition together.
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config ACPI_BERT
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bool "Build ACPI BERT Table"
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default y
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depends on HAVE_ACPI_TABLES
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help
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Report Machine Check errors identified in POST to the OS in an
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ACPI Boot Error Record Table.
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config ACPI_BERT_SIZE
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hex
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default 0x4000 if ACPI_BERT
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default 0x0
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help
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Specify the amount of DRAM reserved for gathering the data used to
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generate the ACPI table.
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endif # SOC_AMD_TURIN_POC
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160
src/soc/amd/turin_poc/Makefile.mk
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160
src/soc/amd/turin_poc/Makefile.mk
Normal file
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@ -0,0 +1,160 @@
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## SPDX-License-Identifier: GPL-2.0-only
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ifeq ($(CONFIG_SOC_AMD_TURIN_POC),y)
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all-y += reset.c
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all-y += config.c
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all-y += gpio.c
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all-y += i2c.c
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all-y += i3c.c
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all-y += uart.c
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bootblock-y += early_fch.c
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bootblock-y += aoac.c
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ramstage-y += acpi.c
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ramstage-y += aoac.c
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ramstage-y += chip.c
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ramstage-y += cpu.c
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ramstage-y += domain.c
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ramstage-y += fch.c
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ramstage-y += root_complex.c
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ramstage-y += smihandler.c
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ramstage-y += mca.c
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smm-y += root_complex.c
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smm-y += smihandler.c
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smm-$(CONFIG_DEBUG_SMI) += uart.c
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CPPFLAGS_common += -I$(src)/soc/amd/turin_poc/acpi
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CPPFLAGS_common += -I$(src)/soc/amd/turin_poc/include
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ifeq ($(call int-gt, $(CONFIG_ROM_SIZE) 0x1000000), 1)
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CBFSTOOL_ADD_CMD_OPTIONS+= --mmap 0:0xff000000:0x1000000
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endif
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#
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# PSP Directory Table items
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#
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# Certain ordering requirements apply, however these are ensured by amdfwtool.
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# For more information see "AMD Platform Security Processor BIOS Implementation
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# Guide for Server EPYC Processors" #57299
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#
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FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}')
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ifeq ($(CONFIG_PSP_DISABLE_POSTCODES),y)
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PSP_SOFTFUSE_BITS += 7
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endif
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ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y)
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# Enable secure debug unlock
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PSP_SOFTFUSE_BITS += 0
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OPT_TOKEN_UNLOCK="--token-unlock"
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endif
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# Use additional Soft Fuse bits specified in Kconfig
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PSP_SOFTFUSE_BITS += $(call strip_quotes, $(CONFIG_PSP_SOFTFUSE_BITS))
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# type = 0x3a
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ifeq ($(CONFIG_HAVE_PSP_WHITELIST_FILE),y)
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PSP_WHITELIST_FILE=$(CONFIG_PSP_WHITELIST_FILE)
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endif
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# type = 0x55
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SPL_TABLE_FILE=$(CONFIG_SPL_TABLE_FILE)
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#
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# BIOS Directory Table items - proper ordering is managed by amdfwtool
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#
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# type = 0x60
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PSP_APCB_FILES=$(APCB_SOURCES) $(APCB1_SOURCES) $(APCB_SOURCES_RECOVERY) $(APCB_SOURCES_RECOVERY1) $(APCB_SOURCES_RECOVERY2)
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# type = 0x61
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PSP_APOB_BASE=$(CONFIG_PSP_APOB_DRAM_ADDRESS)
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# type = 0x62
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PSP_BIOSBIN_FILE=$(obj)/amd_biospsp.img
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PSP_ELF_FILE=$(objcbfs)/bootblock_fixed_data.elf
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PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}')
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PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}')
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# Helper function to return a value with given bit set
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# Soft Fuse type = 0xb - See #57299 (NDA) for bit definitions.
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set-bit=$(call int-shift-left, 1 $(call _toint,$1))
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PSP_SOFTFUSE=$(shell A=$(call int-add, \
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$(foreach bit,$(sort $(PSP_SOFTFUSE_BITS)),$(call set-bit,$(bit)))); printf "0x%x" $$A)
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#
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# Build the arguments to amdfwtool (order is unimportant). Missing file names
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# result in empty OPT_ variables, i.e. the argument is not passed to amdfwtool.
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#
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add_opt_prefix=$(if $(call strip_quotes, $(1)), $(2) $(call strip_quotes, $(1)), )
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OPT_PSP_APCB_FILES= $(if $(APCB_SOURCES), --instance 0 --apcb $(APCB_SOURCES)) \
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$(if $(APCB_SOURCES1), --instance 1 --apcb $(APCB_SOURCES1)) \
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$(if $(APCB_SOURCES_RECOVERY), --instance 10 --apcb $(APCB_SOURCES_RECOVERY)) \
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$(if $(APCB_SOURCES_RECOVERY1), --instance 18 --apcb $(APCB_SOURCES_RECOVERY1)) \
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$(if $(APCB_SOURCES_RECOVERY2), --instance 19 --apcb $(APCB_SOURCES_RECOVERY2)) \
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$(if $(APCB_SOURCES_68), --instance 18 --apcb $(APCB_SOURCES_68))
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OPT_APOB_ADDR=$(call add_opt_prefix, $(PSP_APOB_BASE), --apob-base)
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OPT_PSP_BIOSBIN_FILE=$(call add_opt_prefix, $(PSP_BIOSBIN_FILE), --bios-bin)
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OPT_PSP_BIOSBIN_DEST=$(call add_opt_prefix, $(PSP_BIOSBIN_DEST), --bios-bin-dest)
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OPT_PSP_BIOSBIN_SIZE=$(call add_opt_prefix, $(PSP_BIOSBIN_SIZE), --bios-uncomp-size)
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OPT_EFS_SPI_READ_MODE=$(call add_opt_prefix, $(CONFIG_EFS_SPI_READ_MODE), --spi-read-mode)
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OPT_EFS_SPI_SPEED=$(call add_opt_prefix, $(CONFIG_EFS_SPI_SPEED), --spi-speed)
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OPT_EFS_SPI_MICRON_FLAG=$(call add_opt_prefix, $(CONFIG_EFS_SPI_MICRON_FLAG), --spi-micron-flag)
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OPT_PSP_SOFTFUSE=$(call add_opt_prefix, $(PSP_SOFTFUSE), --soft-fuse)
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OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist)
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OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table)
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AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \
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$(OPT_APOB_ADDR) \
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$(OPT_DEBUG_AMDFWTOOL) \
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$(OPT_PSP_BIOSBIN_FILE) \
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$(OPT_PSP_BIOSBIN_DEST) \
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$(OPT_PSP_BIOSBIN_SIZE) \
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$(OPT_PSP_SOFTFUSE) \
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--use-pspsecureos \
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$(OPT_TOKEN_UNLOCK) \
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$(OPT_WHITELIST_FILE) \
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$(OPT_SPL_TABLE_FILE) \
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$(OPT_EFS_SPI_READ_MODE) \
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$(OPT_EFS_SPI_SPEED) \
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$(OPT_EFS_SPI_MICRON_FLAG) \
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--config $(CONFIG_AMDFW_CONFIG_FILE) \
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--flashsize 0x1000000
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$(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
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$$(PSP_APCB_FILES) \
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$(DEP_FILES) \
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$(AMDFWTOOL) \
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$(obj)/fmap_config.h \
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$(objcbfs)/bootblock_fixed_data.elf # this target also creates the .map file
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$(if $(PSP_APCB_FILES), ,$(error APCB_SOURCES is not set))
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rm -f $@
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@printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n"
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$(AMDFWTOOL) \
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$(AMDFW_COMMON_ARGS) \
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--location $(CONFIG_AMD_FWM_POSITION) \
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--multilevel \
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--output $@
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#
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# Extracts everything from the ELF's first PT_LOAD area and compresses it.
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# This discards everything before PT_LOAD, every symbol, debug information
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# and relocations. The generated binary is expected to run at PSP_BIOSBIN_DEST
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# with a maximum size of PSP_BIOSBIN_SIZE. The entrypoint is fixed at
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# PSP_BIOSBIN_DEST + PSP_BIOSBIN_SIZE - 0x10.
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#
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$(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS)
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rm -f $@
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@printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n"
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$(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \
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--maxsize $(PSP_BIOSBIN_SIZE)
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|
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endif
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66
src/soc/amd/turin_poc/acpi.c
Normal file
66
src/soc/amd/turin_poc/acpi.c
Normal file
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@ -0,0 +1,66 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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|
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/* ACPI - create the Fixed ACPI Description Tables (FADT) */
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#include <acpi/acpi.h>
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#include <amdblocks/acpi.h>
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/cpu.h>
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#include <arch/ioapic.h>
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#include <device/device.h>
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#include <drivers/amd/opensil/opensil.h>
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void acpi_fill_fadt(acpi_fadt_t *fadt)
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{
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/* Fill in pm1_evt, pm1_cnt, pm_tmr, gpe0_blk from openSIL input structure */
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amd_opensil_fill_fadt_io_ports(fadt);
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fadt->pm1_evt_len = 4; /* 32 bits */
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fadt->pm1_cnt_len = 2; /* 16 bits */
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fadt->pm_tmr_len = 4; /* 32 bits */
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fadt->gpe0_blk_len = 8; /* 64 bits */
|
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|
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fill_fadt_extended_pm_io(fadt);
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fadt->iapc_boot_arch = ACPI_FADT_LEGACY_FREE; /* legacy free default */
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fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-34 ACPI 6.3 spec */
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ACPI_FADT_C1_SUPPORTED |
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ACPI_FADT_S4_RTC_WAKE |
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ACPI_FADT_32BIT_TIMER |
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ACPI_FADT_PCI_EXPRESS_WAKE |
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ACPI_FADT_PLATFORM_CLOCK |
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ACPI_FADT_S4_RTC_VALID |
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ACPI_FADT_REMOTE_POWER_ON;
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fadt->x_firmware_ctl_l = 0; /* set to 0 if firmware_ctrl is used */
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fadt->x_firmware_ctl_h = 0;
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}
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||||
|
||||
unsigned long soc_acpi_write_tables(const struct device *device, unsigned long current,
|
||||
struct acpi_rsdp *rsdp)
|
||||
{
|
||||
/* IVRS */
|
||||
current = acpi_add_ivrs_table(current, rsdp);
|
||||
|
||||
return current;
|
||||
}
|
||||
|
||||
/* There are only the following 2 C-states reported by the reference firmware */
|
||||
const acpi_cstate_t cstate_cfg_table[] = {
|
||||
[0] = {
|
||||
.ctype = 1,
|
||||
.latency = 1,
|
||||
.power = 0,
|
||||
},
|
||||
[1] = {
|
||||
.ctype = 2,
|
||||
.latency = 0x12,
|
||||
.power = 0,
|
||||
},
|
||||
};
|
||||
|
||||
const acpi_cstate_t *get_cstate_config_data(size_t *size)
|
||||
{
|
||||
*size = ARRAY_SIZE(cstate_cfg_table);
|
||||
return cstate_cfg_table;
|
||||
}
|
||||
13
src/soc/amd/turin_poc/acpi/globalnvs.asl
Normal file
13
src/soc/amd/turin_poc/acpi/globalnvs.asl
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
/*
|
||||
* NOTE: The layout of the GNVS structure below must match the layout in
|
||||
* soc/amd/turin_poc/include/soc/nvs.h !!!
|
||||
*/
|
||||
|
||||
Field (GNVS, ByteAcc, NoLock, Preserve)
|
||||
{
|
||||
/* Miscellaneous */
|
||||
PM1I, 64, // 0x00 - 0x07 - System Wake Source - PM1 Index
|
||||
GPEI, 64, // 0x08 - 0x0f - GPE Wake Source
|
||||
}
|
||||
414
src/soc/amd/turin_poc/acpi/mmio.asl
Normal file
414
src/soc/amd/turin_poc/acpi/mmio.asl
Normal file
|
|
@ -0,0 +1,414 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/amd/common/acpi/aoac.asl>
|
||||
#include <soc/aoac_defs.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <amdblocks/acpimmio_map.h>
|
||||
|
||||
Device (AAHB)
|
||||
{
|
||||
Name (_HID, "AAHB0000")
|
||||
Name (_UID, 0x0)
|
||||
Name (_CRS, ResourceTemplate()
|
||||
{
|
||||
Memory32Fixed (ReadWrite, ALINK_AHB_ADDRESS, 0x2000)
|
||||
})
|
||||
Name (_STA, 0xb)
|
||||
}
|
||||
|
||||
Device (GPIO)
|
||||
{
|
||||
Name (_HID, GPIO_DEVICE_NAME)
|
||||
Name (_CID, GPIO_DEVICE_NAME)
|
||||
Name (_UID, 0)
|
||||
Name (_DDN, GPIO_DEVICE_DESC)
|
||||
|
||||
Method (_CRS, 0) {
|
||||
Local0 = ResourceTemplate() {
|
||||
Interrupt (
|
||||
ResourceConsumer,
|
||||
Level,
|
||||
ActiveLow,
|
||||
Shared, , , IRQR)
|
||||
{ 0 }
|
||||
Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400)
|
||||
}
|
||||
CreateDWordField (Local0, IRQR._INT, IRQN)
|
||||
If (PICM) {
|
||||
IRQN = IGPI
|
||||
} Else {
|
||||
IRQN = PGPI
|
||||
}
|
||||
If (IRQN == 0x1f || IRQN == 0) {
|
||||
Return (ResourceTemplate() {
|
||||
Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400)
|
||||
})
|
||||
} Else {
|
||||
Return (Local0)
|
||||
}
|
||||
}
|
||||
|
||||
Method (_STA, 0x0, NotSerialized)
|
||||
{
|
||||
Return (0x0F)
|
||||
}
|
||||
}
|
||||
|
||||
Device (FUR0)
|
||||
{
|
||||
Name (_HID, "AMDI0020")
|
||||
Name (_UID, 0x0)
|
||||
Method (_CRS, 0) {
|
||||
Local0 = ResourceTemplate() {
|
||||
Interrupt (
|
||||
ResourceConsumer,
|
||||
Edge,
|
||||
ActiveHigh,
|
||||
Exclusive, , , IRQR)
|
||||
{ 0 }
|
||||
Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000)
|
||||
}
|
||||
CreateDWordField (Local0, IRQR._INT, IRQN)
|
||||
If (PICM) {
|
||||
IRQN = IUA0
|
||||
} Else {
|
||||
IRQN = PUA0
|
||||
}
|
||||
If (IRQN == 0x1f) {
|
||||
Return (ResourceTemplate() {
|
||||
Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000)
|
||||
})
|
||||
} Else {
|
||||
Return (Local0)
|
||||
}
|
||||
}
|
||||
|
||||
Name (STAT, 0x0)
|
||||
Method (_STA, 0x0, NotSerialized)
|
||||
{
|
||||
Return (STAT)
|
||||
}
|
||||
|
||||
AOAC_DEVICE(FCH_AOAC_DEV_UART0, 0)
|
||||
}
|
||||
|
||||
Device (FUR1) {
|
||||
Name (_HID, "AMDI0020")
|
||||
Name (_UID, 0x1)
|
||||
Method (_CRS, 0) {
|
||||
Local0 = ResourceTemplate() {
|
||||
Interrupt (
|
||||
ResourceConsumer,
|
||||
Edge,
|
||||
ActiveHigh,
|
||||
Exclusive, , , IRQR)
|
||||
{ 0 }
|
||||
Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000)
|
||||
}
|
||||
CreateDWordField (Local0, IRQR._INT, IRQN)
|
||||
If (PICM) {
|
||||
IRQN = IUA1
|
||||
} Else {
|
||||
IRQN = PUA1
|
||||
}
|
||||
If (IRQN == 0x1f) {
|
||||
Return (ResourceTemplate() {
|
||||
Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000)
|
||||
})
|
||||
} Else {
|
||||
Return (Local0)
|
||||
}
|
||||
}
|
||||
|
||||
Name (STAT, 0x0)
|
||||
Method (_STA, 0x0, NotSerialized)
|
||||
{
|
||||
Return (STAT)
|
||||
}
|
||||
|
||||
AOAC_DEVICE(FCH_AOAC_DEV_UART1, 0)
|
||||
}
|
||||
|
||||
Device (FUR2) {
|
||||
Name (_HID, "AMDI0020")
|
||||
Name (_UID, 0x2)
|
||||
Method (_CRS, 0) {
|
||||
Local0 = ResourceTemplate() {
|
||||
Interrupt (
|
||||
ResourceConsumer,
|
||||
Edge,
|
||||
ActiveHigh,
|
||||
Exclusive, , , IRQR)
|
||||
{ 0 }
|
||||
Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000)
|
||||
}
|
||||
CreateDWordField (Local0, IRQR._INT, IRQN)
|
||||
If (PICM) {
|
||||
IRQN = IUA2
|
||||
} Else {
|
||||
IRQN = PUA2
|
||||
}
|
||||
If (IRQN == 0x1f) {
|
||||
Return (ResourceTemplate() {
|
||||
Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000)
|
||||
})
|
||||
} Else {
|
||||
Return (Local0)
|
||||
}
|
||||
}
|
||||
|
||||
Name (STAT, 0x0)
|
||||
Method (_STA, 0x0, NotSerialized)
|
||||
{
|
||||
Return (STAT)
|
||||
}
|
||||
|
||||
AOAC_DEVICE(FCH_AOAC_DEV_UART2, 0)
|
||||
}
|
||||
|
||||
Device (I2C0) {
|
||||
Name (_HID, "AMDI0010")
|
||||
Name (_UID, 0x0)
|
||||
Method (_CRS, 0) {
|
||||
Local0 = ResourceTemplate() {
|
||||
Interrupt (
|
||||
ResourceConsumer,
|
||||
Edge,
|
||||
ActiveHigh,
|
||||
Exclusive, , , IRQR)
|
||||
{ 0 }
|
||||
Memory32Fixed (ReadWrite, APU_I2C0_BASE, 0x1000)
|
||||
}
|
||||
CreateDWordField (Local0, IRQR._INT, IRQN)
|
||||
If (PICM) {
|
||||
IRQN = II20
|
||||
} Else {
|
||||
IRQN = PI20
|
||||
}
|
||||
If (IRQN == 0x1f) {
|
||||
Return (ResourceTemplate() {
|
||||
Memory32Fixed (ReadWrite, APU_I2C0_BASE, 0x1000)
|
||||
})
|
||||
} Else {
|
||||
Return (Local0)
|
||||
}
|
||||
}
|
||||
|
||||
Name (STAT, 0x0)
|
||||
Method (_STA, 0x0, NotSerialized)
|
||||
{
|
||||
Return (STAT)
|
||||
}
|
||||
|
||||
AOAC_DEVICE(FCH_AOAC_DEV_I2C0, 0)
|
||||
}
|
||||
|
||||
Device (I2C1) {
|
||||
Name (_HID, "AMDI0010")
|
||||
Name (_UID, 0x1)
|
||||
Method (_CRS, 0) {
|
||||
Local0 = ResourceTemplate() {
|
||||
Interrupt (
|
||||
ResourceConsumer,
|
||||
Edge,
|
||||
ActiveHigh,
|
||||
Exclusive, , , IRQR)
|
||||
{ 0 }
|
||||
Memory32Fixed (ReadWrite, APU_I2C1_BASE, 0x1000)
|
||||
}
|
||||
CreateDWordField (Local0, IRQR._INT, IRQN)
|
||||
If (PICM) {
|
||||
IRQN = II21
|
||||
} Else {
|
||||
IRQN = PI21
|
||||
}
|
||||
If (IRQN == 0x1f) {
|
||||
Return (ResourceTemplate() {
|
||||
Memory32Fixed (ReadWrite, APU_I2C1_BASE, 0x1000)
|
||||
})
|
||||
} Else {
|
||||
Return (Local0)
|
||||
}
|
||||
}
|
||||
|
||||
Name (STAT, 0x0)
|
||||
Method (_STA, 0x0, NotSerialized)
|
||||
{
|
||||
Return (STAT)
|
||||
}
|
||||
|
||||
AOAC_DEVICE(FCH_AOAC_DEV_I2C1, 0)
|
||||
}
|
||||
|
||||
Device (I2C2) {
|
||||
Name (_HID, "AMDI0010")
|
||||
Name (_UID, 0x2)
|
||||
Method (_CRS, 0) {
|
||||
Local0 = ResourceTemplate() {
|
||||
Interrupt (
|
||||
ResourceConsumer,
|
||||
Edge,
|
||||
ActiveHigh,
|
||||
Exclusive, , , IRQR)
|
||||
{ 0 }
|
||||
Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000)
|
||||
}
|
||||
CreateDWordField (Local0, IRQR._INT, IRQN)
|
||||
If (PICM) {
|
||||
IRQN = II22
|
||||
} Else {
|
||||
IRQN = PI22
|
||||
}
|
||||
If (IRQN == 0x1f) {
|
||||
Return (ResourceTemplate() {
|
||||
Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000)
|
||||
})
|
||||
} Else {
|
||||
Return (Local0)
|
||||
}
|
||||
}
|
||||
|
||||
Name (STAT, 0x0)
|
||||
Method (_STA, 0x0, NotSerialized)
|
||||
{
|
||||
Return (STAT)
|
||||
}
|
||||
|
||||
AOAC_DEVICE(FCH_AOAC_DEV_I2C2, 0)
|
||||
}
|
||||
|
||||
Device (I2C3)
|
||||
{
|
||||
Name (_HID, "AMDI0010")
|
||||
Name (_UID, 0x3)
|
||||
Method (_CRS, 0) {
|
||||
Local0 = ResourceTemplate() {
|
||||
Interrupt (
|
||||
ResourceConsumer,
|
||||
Edge,
|
||||
ActiveHigh,
|
||||
Exclusive, , , IRQR)
|
||||
{ 0 }
|
||||
Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000)
|
||||
}
|
||||
CreateDWordField (Local0, IRQR._INT, IRQN)
|
||||
If (PICM) {
|
||||
IRQN = II23
|
||||
} Else {
|
||||
IRQN = PI23
|
||||
}
|
||||
If (IRQN == 0x1f) {
|
||||
Return (ResourceTemplate() {
|
||||
Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000)
|
||||
})
|
||||
} Else {
|
||||
Return (Local0)
|
||||
}
|
||||
}
|
||||
|
||||
Name (STAT, 0x0)
|
||||
Method (_STA, 0x0, NotSerialized)
|
||||
{
|
||||
Return (STAT)
|
||||
}
|
||||
|
||||
AOAC_DEVICE(FCH_AOAC_DEV_I2C3, 0)
|
||||
}
|
||||
|
||||
Device (I2C4)
|
||||
{
|
||||
Name (_HID, "AMDI0010")
|
||||
Name (_UID, 0x4)
|
||||
Method (_CRS, 0) {
|
||||
Local0 = ResourceTemplate() {
|
||||
Interrupt (
|
||||
ResourceConsumer,
|
||||
Edge,
|
||||
ActiveHigh,
|
||||
Exclusive, , , IRQR)
|
||||
{ 0 }
|
||||
Memory32Fixed (ReadWrite, APU_I2C4_BASE, 0x1000)
|
||||
}
|
||||
CreateDWordField (Local0, IRQR._INT, IRQN)
|
||||
If (PICM) {
|
||||
IRQN = II24
|
||||
} Else {
|
||||
IRQN = PI24
|
||||
}
|
||||
If (IRQN == 0x1f) {
|
||||
Return (ResourceTemplate() {
|
||||
Memory32Fixed (ReadWrite, APU_I2C4_BASE, 0x1000)
|
||||
})
|
||||
} Else {
|
||||
Return (Local0)
|
||||
}
|
||||
}
|
||||
|
||||
Name (STAT, 0x0)
|
||||
Method (_STA, 0x0, NotSerialized)
|
||||
{
|
||||
Return (STAT)
|
||||
}
|
||||
|
||||
AOAC_DEVICE(FCH_AOAC_DEV_I2C4, 0)
|
||||
}
|
||||
|
||||
Device (I2C5)
|
||||
{
|
||||
Name (_HID, "AMDI0010")
|
||||
Name (_UID, 0x5)
|
||||
Method (_CRS, 0) {
|
||||
Local0 = ResourceTemplate() {
|
||||
Interrupt (
|
||||
ResourceConsumer,
|
||||
Edge,
|
||||
ActiveHigh,
|
||||
Exclusive, , , IRQR)
|
||||
{ 0 }
|
||||
Memory32Fixed (ReadWrite, APU_I2C5_BASE, 0x1000)
|
||||
}
|
||||
CreateDWordField (Local0, IRQR._INT, IRQN)
|
||||
If (PICM) {
|
||||
IRQN = II25
|
||||
} Else {
|
||||
IRQN = PI25
|
||||
}
|
||||
If (IRQN == 0x1f) {
|
||||
Return (ResourceTemplate() {
|
||||
Memory32Fixed (ReadWrite, APU_I2C5_BASE, 0x1000)
|
||||
})
|
||||
} Else {
|
||||
Return (Local0)
|
||||
}
|
||||
}
|
||||
|
||||
Name (STAT, 0x0)
|
||||
Method (_STA, 0x0, NotSerialized)
|
||||
{
|
||||
Return (STAT)
|
||||
}
|
||||
|
||||
AOAC_DEVICE(FCH_AOAC_DEV_I2C5, 0)
|
||||
}
|
||||
|
||||
Device (MISC)
|
||||
{
|
||||
Name (_HID, "AMD0040")
|
||||
Name (_UID, 0x3)
|
||||
Name (_CRS, ResourceTemplate() {
|
||||
Memory32Fixed (ReadWrite, ACPIMMIO_MISC_BASE, 0x100)
|
||||
})
|
||||
Name (_DSD, Package ()
|
||||
{
|
||||
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
|
||||
Package ()
|
||||
{
|
||||
Package () { "is-rv", 1 },
|
||||
},
|
||||
})
|
||||
Method (_STA, 0x0, NotSerialized)
|
||||
{
|
||||
Return (0x0B)
|
||||
}
|
||||
}
|
||||
98
src/soc/amd/turin_poc/acpi/pci_int_defs.asl
Normal file
98
src/soc/amd/turin_poc/acpi/pci_int_defs.asl
Normal file
|
|
@ -0,0 +1,98 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
/* PCI IRQ mapping registers, C00h-C01h. */
|
||||
OperationRegion(PRQM, SystemIO, 0x00000c00, 0x00000002)
|
||||
Field(PRQM, ByteAcc, NoLock, Preserve) {
|
||||
PRQI, 0x00000008,
|
||||
PRQD, 0x00000008, /* Offset: 1h */
|
||||
}
|
||||
|
||||
/*
|
||||
* All PIC indexes are prefixed with P.
|
||||
* All IO-APIC indexes are prefixed with I.
|
||||
*/
|
||||
IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
|
||||
PIRA, 0x00000008, /* Index 0: INTA */
|
||||
PIRB, 0x00000008, /* Index 1: INTB */
|
||||
PIRC, 0x00000008, /* Index 2: INTC */
|
||||
PIRD, 0x00000008, /* Index 3: INTD */
|
||||
PIRE, 0x00000008, /* Index 4: INTE */
|
||||
PIRF, 0x00000008, /* Index 5: INTF */
|
||||
PIRG, 0x00000008, /* Index 6: INTG */
|
||||
PIRH, 0x00000008, /* Index 7: INTH */
|
||||
|
||||
Offset (0x10),
|
||||
PSCI, 0x00000008, /* Index 0x10: SCI */
|
||||
PSB0, 0x00000008, /* Index 0x11: SMBUS0 */
|
||||
PASF, 0x00000008, /* Index 0x12: ASF */
|
||||
|
||||
Offset (0x16),
|
||||
PPMN, 0x00000008, /* Index 0x16: PerMon */
|
||||
|
||||
Offset (0x1a),
|
||||
PSIO, 0x00000008, /* Index 0x1A: SDIO */
|
||||
|
||||
Offset (0x50),
|
||||
PGP0, 0x00000008, /* Index 0x50: GPP0 */
|
||||
PGP1, 0x00000008, /* Index 0x51: GPP1 */
|
||||
PGP2, 0x00000008, /* Index 0x52: GPP2 */
|
||||
PGP3, 0x00000008, /* Index 0x53: GPP3 */
|
||||
|
||||
Offset (0x62),
|
||||
PGPI, 0x00000008, /* Index 0x62: GPIO */
|
||||
|
||||
Offset (0x70),
|
||||
PI20, 0x00000008, /* Index 0x70: I2C0/I3C0 */
|
||||
PI21, 0x00000008, /* Index 0x71: I2C1/I3C1 */
|
||||
PI22, 0x00000008, /* Index 0x72: I2C2/I3C2 */
|
||||
PI23, 0x00000008, /* Index 0x73: I2C3/I3C3 */
|
||||
PUA0, 0x00000008, /* Index 0x74: UART0 */
|
||||
PUA1, 0x00000008, /* Index 0x75: UART1 */
|
||||
PI24, 0x00000008, /* Index 0x76: I2C4 */
|
||||
PI25, 0x00000008, /* Index 0x77: I2C5 */
|
||||
PUA2, 0x00000008, /* Index 0x78: UART2 */
|
||||
PUA3, 0x00000008, /* Index 0x79: UART3 */
|
||||
|
||||
/* IO-APIC IRQs */
|
||||
Offset (0x80),
|
||||
IORA, 0x00000008, /* Index 0x80: INTA */
|
||||
IORB, 0x00000008, /* Index 0x81: INTB */
|
||||
IORC, 0x00000008, /* Index 0x82: INTC */
|
||||
IORD, 0x00000008, /* Index 0x83: INTD */
|
||||
IORE, 0x00000008, /* Index 0x84: INTE */
|
||||
IORF, 0x00000008, /* Index 0x85: INTF */
|
||||
IORG, 0x00000008, /* Index 0x86: INTG */
|
||||
IORH, 0x00000008, /* Index 0x87: INTH */
|
||||
|
||||
Offset (0x90),
|
||||
ISCI, 0x00000008, /* Index 0x90: SCI */
|
||||
ISB0, 0x00000008, /* Index 0x91: SMBUS0 */
|
||||
IASF, 0x00000008, /* Index 0x92: ASF */
|
||||
|
||||
Offset (0x96),
|
||||
IPMN, 0x00000008, /* Index 0x96: PerMon */
|
||||
|
||||
Offset (0x9a),
|
||||
ISIO, 0x00000008, /* Index 0x9A: SDIO */
|
||||
|
||||
Offset (0xD0),
|
||||
IGP0, 0x00000008, /* Index 0xD0: GPP0 */
|
||||
IGP1, 0x00000008, /* Index 0xD1: GPP1 */
|
||||
IGP2, 0x00000008, /* Index 0xD2: GPP2 */
|
||||
IGP3, 0x00000008, /* Index 0xD3: GPP3 */
|
||||
|
||||
Offset (0xE2),
|
||||
IGPI, 0x00000008, /* Index 0xE2: GPIO */
|
||||
|
||||
Offset (0xF0),
|
||||
II20, 0x00000008, /* Index 0xF0: I2C0/I3C0 */
|
||||
II21, 0x00000008, /* Index 0xF1: I2C1/I3C1 */
|
||||
II22, 0x00000008, /* Index 0xF2: I2C2/I3C2 */
|
||||
II23, 0x00000008, /* Index 0xF3: I2C3/I3C3 */
|
||||
IUA0, 0x00000008, /* Index 0xF4: UART0 */
|
||||
IUA1, 0x00000008, /* Index 0xF5: UART1 */
|
||||
II24, 0x00000008, /* Index 0xF6: I2C4 */
|
||||
II25, 0x00000008, /* Index 0xF7: I2C5 */
|
||||
IUA2, 0x00000008, /* Index 0xF8: UART2 */
|
||||
IUA3, 0x00000008, /* Index 0xF9: UART3 */
|
||||
}
|
||||
39
src/soc/amd/turin_poc/acpi/soc.asl
Normal file
39
src/soc/amd/turin_poc/acpi/soc.asl
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/amd/common/acpi/pci_root.asl>
|
||||
#include "globalnvs.asl"
|
||||
|
||||
Scope(\_SB) {
|
||||
/* global utility methods expected within the \_SB scope */
|
||||
#include <arch/x86/acpi/globutil.asl>
|
||||
|
||||
#include <soc/amd/common/acpi/gpio_bank_lib.asl>
|
||||
|
||||
#include <soc/amd/common/acpi/osc.asl>
|
||||
|
||||
#include "pci_int_defs.asl"
|
||||
|
||||
#include "mmio.asl"
|
||||
|
||||
ROOT_BRIDGE(S0B0)
|
||||
ROOT_BRIDGE(S0B1)
|
||||
ROOT_BRIDGE(S0B2)
|
||||
ROOT_BRIDGE(S0B3)
|
||||
} /* End \_SB scope */
|
||||
|
||||
#include <soc/amd/common/acpi/alib.asl>
|
||||
|
||||
#include <soc/amd/common/acpi/platform.asl>
|
||||
|
||||
#include <soc/amd/common/acpi/sleepstates.asl>
|
||||
|
||||
/*
|
||||
* Platform Notify
|
||||
*
|
||||
* This is called by soc/amd/common/acpi/platform.asl.
|
||||
*/
|
||||
Method (PNOT)
|
||||
{
|
||||
/* Report AC/DC state to ALIB using WAL1() */
|
||||
\WAL1 ()
|
||||
}
|
||||
32
src/soc/amd/turin_poc/aoac.c
Normal file
32
src/soc/amd/turin_poc/aoac.c
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <stdint.h>
|
||||
#include <amdblocks/acpimmio.h>
|
||||
#include <amdblocks/aoac.h>
|
||||
#include <soc/aoac_defs.h>
|
||||
#include <soc/southbridge.h>
|
||||
#include <delay.h>
|
||||
|
||||
#define FCH_AOAC_UART_FOR_CONSOLE \
|
||||
(CONFIG_UART_FOR_CONSOLE == 0 ? FCH_AOAC_DEV_UART0 \
|
||||
: CONFIG_UART_FOR_CONSOLE == 1 ? FCH_AOAC_DEV_UART1 \
|
||||
: CONFIG_UART_FOR_CONSOLE == 2 ? FCH_AOAC_DEV_UART2 \
|
||||
: -1)
|
||||
#if CONFIG(AMD_SOC_CONSOLE_UART) && FCH_AOAC_UART_FOR_CONSOLE == -1
|
||||
# error Unsupported UART_FOR_CONSOLE chosen
|
||||
#endif
|
||||
|
||||
void wait_for_aoac_enabled(unsigned int dev)
|
||||
{
|
||||
while (!is_aoac_device_enabled(dev))
|
||||
udelay(100);
|
||||
}
|
||||
|
||||
void enable_aoac_devices(void)
|
||||
{
|
||||
if (CONFIG(AMD_SOC_CONSOLE_UART))
|
||||
power_on_aoac_device(FCH_AOAC_UART_FOR_CONSOLE);
|
||||
|
||||
if (CONFIG(AMD_SOC_CONSOLE_UART))
|
||||
wait_for_aoac_enabled(FCH_AOAC_UART_FOR_CONSOLE);
|
||||
}
|
||||
28
src/soc/amd/turin_poc/chip.c
Normal file
28
src/soc/amd/turin_poc/chip.c
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <amdblocks/acpi.h>
|
||||
#include <amdblocks/data_fabric.h>
|
||||
#include <device/device.h>
|
||||
#include <drivers/amd/opensil/opensil.h>
|
||||
#include <soc/southbridge.h>
|
||||
|
||||
static void soc_init(void *chip_info)
|
||||
{
|
||||
default_dev_ops_root.write_acpi_tables = soc_acpi_write_tables;
|
||||
|
||||
amd_opensil_silicon_init();
|
||||
|
||||
data_fabric_print_mmio_conf();
|
||||
|
||||
fch_init(chip_info);
|
||||
}
|
||||
|
||||
static void soc_final(void *chip_info)
|
||||
{
|
||||
}
|
||||
|
||||
struct chip_operations soc_amd_turin_poc_ops = {
|
||||
.name = "AMD Turin SoC Proof of Concept",
|
||||
.init = soc_init,
|
||||
.final = soc_final,
|
||||
};
|
||||
71
src/soc/amd/turin_poc/chip.h
Normal file
71
src/soc/amd/turin_poc/chip.h
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef __TURIN_POC_CHIP_H__
|
||||
#define __TURIN_POC_CHIP_H__
|
||||
|
||||
#include <amdblocks/chip.h>
|
||||
#include <amdblocks/i2c.h>
|
||||
#include <drivers/i2c/designware/dw_i2c.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <types.h>
|
||||
|
||||
struct usb31_phy_settings {
|
||||
uint8_t rx_ana_iq_phase_adjust;
|
||||
uint8_t rx_eq_delta_iq_ovrd_en;
|
||||
uint8_t rx_eq_delta_iq_ovrd_val;
|
||||
uint8_t rx_iq_phase_adjust;
|
||||
uint8_t tx_vboost_lvl_en;
|
||||
uint8_t tx_vboost_lvl;
|
||||
uint8_t rx_vref_ctrl_en;
|
||||
uint8_t rx_vref_ctrl;
|
||||
uint8_t tx_vboost_lvl_en_x;
|
||||
uint8_t tx_vboost_lvl_x;
|
||||
uint8_t rx_vref_ctrl_en_x;
|
||||
uint8_t rx_vref_ctrl_x;
|
||||
};
|
||||
|
||||
struct soc_usb_config {
|
||||
uint8_t xhci0_enable : 1;
|
||||
uint8_t xhci1_enable : 1;
|
||||
struct {
|
||||
uint8_t port0 : 4;
|
||||
uint8_t port1 : 4;
|
||||
uint8_t port2 : 4;
|
||||
uint8_t port3 : 4;
|
||||
uint8_t port4 : 4;
|
||||
uint8_t port5 : 4;
|
||||
uint8_t port6 : 4;
|
||||
uint8_t port7 : 4;
|
||||
} usb2_oc_pins[2];
|
||||
struct {
|
||||
uint8_t port0 : 4;
|
||||
uint8_t port1 : 4;
|
||||
uint8_t port2 : 4;
|
||||
uint8_t port3 : 4;
|
||||
} usb3_oc_pins[2];
|
||||
bool polarity_cfg_low;
|
||||
union {
|
||||
struct {
|
||||
uint8_t port0 : 2;
|
||||
uint8_t port1 : 2;
|
||||
uint8_t port2 : 2; /* Broken in OpenSIL */
|
||||
uint8_t port3 : 2; /* Broken in OpenSIL */
|
||||
};
|
||||
uint8_t raw;
|
||||
} usb3_force_gen1;
|
||||
bool usb31_phy_enable;
|
||||
struct usb31_phy_settings usb31_phy[8];
|
||||
bool s1_usb31_phy_enable;
|
||||
struct usb31_phy_settings s1_usb31_phy[8];
|
||||
};
|
||||
|
||||
struct soc_amd_turin_poc_config {
|
||||
struct soc_amd_common_config common_config;
|
||||
|
||||
u8 i2c_scl_reset;
|
||||
struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT];
|
||||
|
||||
struct soc_usb_config usb;
|
||||
};
|
||||
|
||||
#endif /* __TURIN_POC_CHIP_H__ */
|
||||
394
src/soc/amd/turin_poc/chipset.cb
Normal file
394
src/soc/amd/turin_poc/chipset.cb
Normal file
|
|
@ -0,0 +1,394 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/amd/turin_poc
|
||||
device cpu_cluster 0 on ops amd_cpu_bus_ops end
|
||||
|
||||
# OC pins
|
||||
register "usb.usb2_oc_pins[0]" = "{ 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }"
|
||||
register "usb.usb2_oc_pins[1]" = "{ 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf }"
|
||||
register "usb.usb3_oc_pins[0]" = "{ 0xf, 0xf, 0xf, 0xf }"
|
||||
register "usb.usb3_oc_pins[1]" = "{ 0xf, 0xf, 0xf, 0xf }"
|
||||
|
||||
device domain 0 on
|
||||
ops turin_pci_domain_ops
|
||||
device pci 00.0 alias gnb_0 on end
|
||||
device pci 00.2 alias iommu_0 off ops amd_iommu_ops end
|
||||
device pci 00.3 alias rcec_0 off end
|
||||
|
||||
device pci 01.0 on end # Dummy device function, do not disable
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.1 alias gpp_bridge_0_0_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.2 alias gpp_bridge_0_1_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.3 alias gpp_bridge_0_2_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.4 alias gpp_bridge_0_3_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.5 alias gpp_bridge_0_4_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.6 alias gpp_bridge_0_5_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.7 alias gpp_bridge_0_6_a off end
|
||||
end
|
||||
|
||||
device pci 02.0 on end # Dummy device function, do not disable
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 02.1 alias gpp_bridge_0_7_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 02.2 alias gpp_bridge_0_8_a off end
|
||||
end
|
||||
|
||||
device pci 03.0 on end # Dummy device function, do not disable
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.1 alias gpp_bridge_0_0_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.2 alias gpp_bridge_0_1_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.3 alias gpp_bridge_0_2_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.4 alias gpp_bridge_0_3_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.5 alias gpp_bridge_0_4_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.6 alias gpp_bridge_0_5_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.7 alias gpp_bridge_0_6_b off end
|
||||
end
|
||||
|
||||
device pci 04.0 on end # Dummy device function, do not disable
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 04.1 alias gpp_bridge_0_7_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 04.2 alias gpp_bridge_0_8_b off end
|
||||
end
|
||||
|
||||
device pci 05.0 on end # Dummy device function, do not disable
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 05.1 alias gpp_bridge_0_0_c off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 05.2 alias gpp_bridge_0_1_c off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 05.3 alias gpp_bridge_0_2_c off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 05.4 alias gpp_bridge_0_3_c off end
|
||||
end
|
||||
|
||||
device pci 07.0 on end # Dummy device function, do not disable
|
||||
device pci 07.1 alias gpp_bridge_0_a off # Internal GPP Bridge 0 to Bus B0
|
||||
device pci 0.0 on end # Dummy PCIe function
|
||||
device pci 0.1 off end
|
||||
device pci 0.2 alias primary_NTB_0 off end # Primary PCIe Non-TransparentBridge
|
||||
device pci 0.3 alias secondry_NTB_0 off end # Secondary vNTB
|
||||
device pci 0.4 alias xhci_0 off end # USB
|
||||
device pci 0.5 alias mp0_0 off end # PSP (MP0)
|
||||
device pci 0.6 alias acp_0 off end # Audio Processor (ACP)
|
||||
device pci 0.7 alias hda_0 off end # Audio Processor HD Audio Controller (main AZ)
|
||||
end
|
||||
device pci 07.2 alias gpp_bridge_0_b off # Internal GPP Bridge 1 to Bus C0
|
||||
device pci 0.0 alias sata_0_0 off end # first SATA controller; AHCI mode
|
||||
device pci 0.1 alias sata_0_1 off end # second SATA controller; AHCI mode
|
||||
end
|
||||
|
||||
device pci 14.0 alias smbus on end # primary FCH function
|
||||
device pci 14.3 alias lpc_bridge on ops amd_lpc_ops end
|
||||
device pci 14.6 alias sdhci off end
|
||||
|
||||
device pci 18.0 alias data_fabric_0 on end
|
||||
device pci 18.1 alias data_fabric_1 on end
|
||||
device pci 18.2 alias data_fabric_2 on end
|
||||
device pci 18.3 alias data_fabric_3 on end
|
||||
device pci 18.4 alias data_fabric_4 on end
|
||||
device pci 18.5 alias data_fabric_5 on end
|
||||
device pci 18.6 alias data_fabric_6 on end
|
||||
device pci 18.7 alias data_fabric_7 on end
|
||||
end
|
||||
|
||||
device domain 1 on
|
||||
ops turin_pci_domain_ops
|
||||
device pci 00.0 alias gnb_1 on end
|
||||
device pci 00.2 alias iommu_1 off ops amd_iommu_ops end
|
||||
device pci 00.3 alias rcec_1 off end
|
||||
|
||||
device pci 01.0 on end # Dummy device function, do not disable
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.1 alias gpp_bridge_1_0_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.2 alias gpp_bridge_1_1_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.3 alias gpp_bridge_1_2_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.4 alias gpp_bridge_1_3_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.5 alias gpp_bridge_1_4_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.6 alias gpp_bridge_1_5_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.7 alias gpp_bridge_1_6_a off end
|
||||
end
|
||||
|
||||
device pci 02.0 on end # Dummy device function, do not disable
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 02.1 alias gpp_bridge_1_7_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 02.2 alias gpp_bridge_1_8_a off end
|
||||
end
|
||||
|
||||
device pci 03.0 on end # Dummy device function, do not disable
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.1 alias gpp_bridge_1_0_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.2 alias gpp_bridge_1_1_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.3 alias gpp_bridge_1_2_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.4 alias gpp_bridge_1_3_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.5 alias gpp_bridge_1_4_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.6 alias gpp_bridge_1_5_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.7 alias gpp_bridge_1_6_b off end
|
||||
end
|
||||
|
||||
device pci 04.0 on end # Dummy device function, do not disable
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 04.1 alias gpp_bridge_1_7_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 04.2 alias gpp_bridge_1_8_b off end
|
||||
end
|
||||
|
||||
device pci 05.0 on end # Dummy device function, do not disable
|
||||
|
||||
device pci 07.0 on end # Dummy device function, do not disable
|
||||
device pci 07.1 alias gpp_bridge_1_a off
|
||||
device pci 0.0 on end # Dummy PCIe function
|
||||
device pci 0.1 off end #SDXI
|
||||
device pci 0.2 alias primary_NTB_1 off end # Primary PCIe Non-TransparentBridge
|
||||
device pci 0.3 alias secondry_NTB_1 off end # Secondary vNTB
|
||||
end
|
||||
end
|
||||
|
||||
device domain 2 on
|
||||
ops turin_pci_domain_ops
|
||||
device pci 00.0 alias gnb_2 on end
|
||||
device pci 00.2 alias iommu_2 off ops amd_iommu_ops end
|
||||
device pci 00.3 alias rcec_2 off end
|
||||
|
||||
device pci 01.0 on end # Dummy device function, do not disable
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.1 alias gpp_bridge_2_0_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.2 alias gpp_bridge_2_1_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.3 alias gpp_bridge_2_2_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.4 alias gpp_bridge_2_3_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.5 alias gpp_bridge_2_4_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.6 alias gpp_bridge_2_5_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.7 alias gpp_bridge_2_6_a off end
|
||||
end
|
||||
|
||||
device pci 02.0 on end # Dummy device function, do not disable
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 02.1 alias gpp_bridge_2_7_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 02.2 alias gpp_bridge_2_8_a off end
|
||||
end
|
||||
|
||||
device pci 03.0 on end # Dummy device function, do not disable
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.1 alias gpp_bridge_2_0_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.2 alias gpp_bridge_2_1_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.3 alias gpp_bridge_2_2_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.4 alias gpp_bridge_2_3_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.5 alias gpp_bridge_2_4_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.6 alias gpp_bridge_2_5_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.7 alias gpp_bridge_2_6_b off end
|
||||
end
|
||||
|
||||
device pci 04.0 on end # Dummy device function, do not disable
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 04.1 alias gpp_bridge_2_7_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 04.2 alias gpp_bridge_2_8_b off end
|
||||
end
|
||||
|
||||
device pci 05.0 on end # Dummy device function, do not disable
|
||||
|
||||
device pci 07.0 on end # Dummy device function, do not disable
|
||||
device pci 07.1 alias gpp_bridge_2_a off
|
||||
device pci 0.0 on end # Dummy PCIe function
|
||||
device pci 0.1 off end
|
||||
device pci 0.2 alias primary_NTB_2 off end # Primary PCIe Non-TransparentBridge
|
||||
device pci 0.3 alias secondry_NTB_2 off end # Secondary vNTB
|
||||
end
|
||||
end
|
||||
|
||||
device domain 3 on
|
||||
ops turin_pci_domain_ops
|
||||
device pci 00.0 alias gnb_3 on end
|
||||
device pci 00.2 alias iommu_3 off ops amd_iommu_ops end
|
||||
device pci 00.3 alias rcec_3 off end
|
||||
|
||||
device pci 01.0 on end # Dummy device function, do not disable
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.1 alias gpp_bridge_3_0_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.2 alias gpp_bridge_3_1_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.3 alias gpp_bridge_3_2_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.4 alias gpp_bridge_3_3_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.5 alias gpp_bridge_3_4_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.6 alias gpp_bridge_3_5_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 01.7 alias gpp_bridge_3_6_a off end
|
||||
end
|
||||
|
||||
device pci 02.0 on end # Dummy device function, do not disable
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 02.1 alias gpp_bridge_3_7_a off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 02.2 alias gpp_bridge_3_8_a off end
|
||||
end
|
||||
|
||||
device pci 03.0 on end # Dummy device function, do not disable
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.1 alias gpp_bridge_3_0_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.2 alias gpp_bridge_3_1_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.3 alias gpp_bridge_3_2_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.4 alias gpp_bridge_3_3_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.5 alias gpp_bridge_3_4_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.6 alias gpp_bridge_3_5_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 03.7 alias gpp_bridge_3_6_b off end
|
||||
end
|
||||
|
||||
device pci 04.0 on end # Dummy device function, do not disable
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 04.1 alias gpp_bridge_3_7_b off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 04.2 alias gpp_bridge_3_8_b off end
|
||||
end
|
||||
|
||||
device pci 05.0 on end # Dummy device function, do not disable
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 05.1 alias gpp_bridge_3_0_c off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 05.2 alias gpp_bridge_3_1_c off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 05.3 alias gpp_bridge_3_2_c off end
|
||||
end
|
||||
chip drivers/amd/opensil/mpio
|
||||
device pci 05.4 alias gpp_bridge_3_3_c off end
|
||||
end
|
||||
|
||||
device pci 07.0 on end # Dummy device function, do not disable
|
||||
device pci 07.1 alias gpp_bridge_3_a off
|
||||
device pci 0.0 on end # Dummy PCIe function
|
||||
device pci 0.1 off end #SDXI
|
||||
device pci 0.2 alias primary_NTB_3 off end # Primary PCIe Non-TransparentBridge
|
||||
device pci 0.3 alias secondry_NTB_3 off end # Secondary vNTB
|
||||
device pci 0.4 alias xhci_3 off end # USB
|
||||
device pci 0.5 alias mp0_3 off end # PSP (MP0)
|
||||
end
|
||||
|
||||
device pci 07.2 alias gpp_bridge_3_b off
|
||||
device pci 0.0 alias sata_3_0 off end # first SATA controller; AHCI mode
|
||||
device pci 0.1 alias sata_3_1 off end # second SATA controller; AHCI mode
|
||||
end
|
||||
end
|
||||
|
||||
device mmio 0xfedc2000 alias i2c_0 off ops soc_amd_i2c_mmio_ops end
|
||||
device mmio 0xfedc3000 alias i2c_1 off ops soc_amd_i2c_mmio_ops end
|
||||
device mmio 0xfedc4000 alias i2c_2 off ops soc_amd_i2c_mmio_ops end
|
||||
device mmio 0xfedc5000 alias i2c_3 off ops soc_amd_i2c_mmio_ops end
|
||||
device mmio 0xfedc6000 alias i2c_4 off ops soc_amd_i2c_mmio_ops end
|
||||
device mmio 0xfedcb000 alias i2c_5 off ops soc_amd_i2c_mmio_ops end
|
||||
device mmio 0xfedc9000 alias uart_0 off ops amd_uart_mmio_ops end
|
||||
device mmio 0xfedca000 alias uart_1 off ops amd_uart_mmio_ops end
|
||||
device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end
|
||||
device mmio 0xfedd2000 alias i3c_0 off ops soc_amd_i3c_mmio_ops end
|
||||
device mmio 0xfedd3000 alias i3c_1 off ops soc_amd_i3c_mmio_ops end
|
||||
device mmio 0xfedd4000 alias i3c_2 off ops soc_amd_i3c_mmio_ops end
|
||||
device mmio 0xfedd6000 alias i3c_3 off ops soc_amd_i3c_mmio_ops end
|
||||
|
||||
end
|
||||
12
src/soc/amd/turin_poc/config.c
Normal file
12
src/soc/amd/turin_poc/config.c
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <amdblocks/chip.h>
|
||||
#include <device/device.h>
|
||||
#include <static.h>
|
||||
#include "chip.h"
|
||||
|
||||
const struct soc_amd_common_config *soc_get_common_config(void)
|
||||
{
|
||||
const struct soc_amd_turin_poc_config *cfg = config_of_soc();
|
||||
return &cfg->common_config;
|
||||
}
|
||||
21
src/soc/amd/turin_poc/cpu.c
Normal file
21
src/soc/amd/turin_poc/cpu.c
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <amdblocks/cpu.h>
|
||||
#include <cpu/cpu.h>
|
||||
#include <device/device.h>
|
||||
#include <soc/cpu.h>
|
||||
|
||||
static struct device_operations cpu_dev_ops = {
|
||||
.init = amd_cpu_init,
|
||||
};
|
||||
|
||||
static struct cpu_device_id cpu_table[] = {
|
||||
{ X86_VENDOR_AMD, TURIN_A0_CPUID, CPUID_ALL_STEPPINGS_MASK },
|
||||
{ X86_VENDOR_AMD, TURIN_B0_CPUID, CPUID_ALL_STEPPINGS_MASK },
|
||||
CPU_TABLE_END
|
||||
};
|
||||
|
||||
static const struct cpu_driver model_19 __cpu_driver = {
|
||||
.ops = &cpu_dev_ops,
|
||||
.id_table = cpu_table,
|
||||
};
|
||||
71
src/soc/amd/turin_poc/domain.c
Normal file
71
src/soc/amd/turin_poc/domain.c
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <acpi/acpigen_pci.h>
|
||||
#include <amdblocks/ioapic.h>
|
||||
#include <amdblocks/data_fabric.h>
|
||||
#include <amdblocks/memmap.h>
|
||||
#include <amdblocks/root_complex.h>
|
||||
#include <amdblocks/smn.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <drivers/amd/opensil/opensil.h>
|
||||
#include <types.h>
|
||||
|
||||
#define IOHC_IOAPIC_BASE_ADDR_LO 0x2f0
|
||||
|
||||
void read_soc_memmap_resources(struct device *domain, unsigned long *idx)
|
||||
{
|
||||
read_lower_soc_memmap_resources(domain, idx);
|
||||
|
||||
amd_opensil_add_memmap(domain, idx);
|
||||
}
|
||||
|
||||
static void turin_domain_set_resources(struct device *domain)
|
||||
{
|
||||
if (domain->downstream->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
|
||||
printk(BIOS_DEBUG, "Setting VGA decoding for domain 0x%x\n",
|
||||
dev_get_domain_id(domain));
|
||||
const union df_vga_en vga_en = {
|
||||
.ve = 1,
|
||||
.dst_fabric_id = get_iohc_fabric_id(domain),
|
||||
};
|
||||
data_fabric_broadcast_write32(DF_VGA_EN, vga_en.raw);
|
||||
}
|
||||
|
||||
pci_domain_set_resources(domain);
|
||||
|
||||
/* Enable IOAPIC memory decoding */
|
||||
struct resource *res = probe_resource(domain, IOMMU_IOAPIC_IDX);
|
||||
if (res) {
|
||||
const uint32_t iohc_misc_base = get_iohc_misc_smn_base(domain);
|
||||
uint32_t ioapic_base = smn_read32(iohc_misc_base | IOHC_IOAPIC_BASE_ADDR_LO);
|
||||
ioapic_base |= (1 << 0);
|
||||
smn_write32(iohc_misc_base | IOHC_IOAPIC_BASE_ADDR_LO, ioapic_base);
|
||||
}
|
||||
}
|
||||
|
||||
static const char *turin_domain_acpi_name(const struct device *domain)
|
||||
{
|
||||
const unsigned int domain_id = dev_get_domain_id(domain);
|
||||
const char *domain_acpi_names[4] = {
|
||||
"S0B0",
|
||||
"S0B1",
|
||||
"S0B2",
|
||||
"S0B3",
|
||||
};
|
||||
|
||||
if (domain_id < ARRAY_SIZE(domain_acpi_names))
|
||||
return domain_acpi_names[domain_id];
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
struct device_operations turin_pci_domain_ops = {
|
||||
.read_resources = amd_pci_domain_read_resources,
|
||||
.set_resources = turin_domain_set_resources,
|
||||
.scan_bus = amd_pci_domain_scan_bus,
|
||||
.init = amd_pci_domain_init,
|
||||
.acpi_name = turin_domain_acpi_name,
|
||||
.acpi_fill_ssdt = pci_domain_fill_ssdt,
|
||||
};
|
||||
33
src/soc/amd/turin_poc/early_fch.c
Normal file
33
src/soc/amd/turin_poc/early_fch.c
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <amdblocks/espi.h>
|
||||
#include <amdblocks/lpc.h>
|
||||
#include <amdblocks/acpimmio.h>
|
||||
#include <amdblocks/aoac.h>
|
||||
#include <amdblocks/pmlib.h>
|
||||
#include <amdblocks/uart.h>
|
||||
#include <soc/southbridge.h>
|
||||
#include <soc/uart.h>
|
||||
|
||||
/* Before console init */
|
||||
void fch_pre_init(void)
|
||||
{
|
||||
fch_enable_cf9_io();
|
||||
|
||||
enable_aoac_devices();
|
||||
/*
|
||||
* On reset Range_0 defaults to enabled. We want to start with a clean
|
||||
* slate to not have things unexpectedly enabled.
|
||||
*/
|
||||
clear_uart_legacy_config();
|
||||
|
||||
if (CONFIG(AMD_SOC_CONSOLE_UART))
|
||||
set_uart_config(CONFIG_UART_FOR_CONSOLE);
|
||||
|
||||
configure_espi_with_mb_hook();
|
||||
}
|
||||
|
||||
/* After console init */
|
||||
void fch_early_init(void)
|
||||
{
|
||||
}
|
||||
86
src/soc/amd/turin_poc/fch.c
Normal file
86
src/soc/amd/turin_poc/fch.c
Normal file
|
|
@ -0,0 +1,86 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <amdblocks/acpi.h>
|
||||
#include <amdblocks/acpimmio.h>
|
||||
#include <amdblocks/amd_pci_util.h>
|
||||
#include <amdblocks/gpio.h>
|
||||
#include <amdblocks/smi.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <soc/amd_pci_int_defs.h>
|
||||
#include <soc/smi.h>
|
||||
#include <soc/southbridge.h>
|
||||
|
||||
/*
|
||||
* Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME
|
||||
* provides a visible association with the index, therefore helping
|
||||
* maintainability of table. If a new index/name is defined in
|
||||
* amd_pci_int_defs.h, just add the pair at the end of this table.
|
||||
* Order is not important.
|
||||
*/
|
||||
static const struct irq_idx_name irq_association[] = {
|
||||
{ PIRQ_A, "INTA#" },
|
||||
{ PIRQ_B, "INTB#" },
|
||||
{ PIRQ_C, "INTC#" },
|
||||
{ PIRQ_D, "INTD#" },
|
||||
{ PIRQ_E, "INTE#" },
|
||||
{ PIRQ_F, "INTF#/GENINT2" },
|
||||
{ PIRQ_G, "INTG#" },
|
||||
{ PIRQ_H, "INTH#" },
|
||||
{ PIRQ_MISC, "Misc" },
|
||||
{ PIRQ_MISC0, "Misc0" },
|
||||
{ PIRQ_HPET_L, "HPET_L" },
|
||||
{ PIRQ_HPET_H, "HPET_H" },
|
||||
{ PIRQ_SIRQA, "Ser IRQ INTA" },
|
||||
{ PIRQ_SIRQB, "Ser IRQ INTB" },
|
||||
{ PIRQ_SIRQC, "Ser IRQ INTC" },
|
||||
{ PIRQ_SIRQD, "Ser IRQ INTD" },
|
||||
{ PIRQ_SCI, "SCI" },
|
||||
{ PIRQ_SMBUS, "SMBUS" },
|
||||
{ PIRQ_ASF, "ASF" },
|
||||
{ PIRQ_PMON, "PerMon" },
|
||||
{ PIRQ_SDIO, "SDIO" },
|
||||
{ PIRQ_GPP0, "GPP0" },
|
||||
{ PIRQ_GPP1, "GPP1" },
|
||||
{ PIRQ_GPP2, "GPP2" },
|
||||
{ PIRQ_GPP3, "GPP3" },
|
||||
{ PIRQ_GSCI, "GEvent SCI" },
|
||||
{ PIRQ_GSMI, "GEvent SMI" },
|
||||
{ PIRQ_GPIO, "GPIO" },
|
||||
{ PIRQ_I2C0, "I2C0" },
|
||||
{ PIRQ_I2C1, "I2C1" },
|
||||
{ PIRQ_I2C2, "I2C2" },
|
||||
{ PIRQ_I2C3, "I2C3" },
|
||||
{ PIRQ_UART0, "UART0" },
|
||||
{ PIRQ_UART1, "UART1" },
|
||||
{ PIRQ_I2C4, "I2C4" },
|
||||
{ PIRQ_I2C5, "I2C5" },
|
||||
{ PIRQ_UART2, "UART2" },
|
||||
{ PIRQ_UART3, "UART3" },
|
||||
};
|
||||
|
||||
const struct irq_idx_name *sb_get_apic_reg_association(size_t *size)
|
||||
{
|
||||
*size = ARRAY_SIZE(irq_association);
|
||||
return irq_association;
|
||||
}
|
||||
|
||||
static void set_pci_irqs(void)
|
||||
{
|
||||
/* Write PCI_INTR regs 0xC00/0xC01 */
|
||||
write_pci_int_table();
|
||||
|
||||
/* TODO: PIRQ configuration */
|
||||
}
|
||||
|
||||
static void fch_init_acpi_ports(void)
|
||||
{
|
||||
/* Configure and enable APMC SMI Command Port */
|
||||
pm_write16(PM_ACPI_SMI_CMD, APM_CNT);
|
||||
configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI);
|
||||
}
|
||||
|
||||
void fch_init(void *chip_info)
|
||||
{
|
||||
set_pci_irqs();
|
||||
fch_init_acpi_ports();
|
||||
}
|
||||
54
src/soc/amd/turin_poc/fw.cfg
Normal file
54
src/soc/amd/turin_poc/fw.cfg
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
# PSP fw config file
|
||||
FIRMWARE_LOCATION 3rdparty/amd_blobs/turin/PSP
|
||||
SOC_NAME Turin
|
||||
|
||||
# type file
|
||||
# PSP
|
||||
AMD_PUBKEY_FILE Typex0_0_0_0_AmdPubKey.bin
|
||||
PSPBTLDR_FILE Typex1_0_0_0_PspBootLoader.bin Lbb
|
||||
PSPRCVR_FILE Typex3_0_0_0_PspRecBL.bin
|
||||
PSP_SMUFW1_SUB0_FILE Typex8_0_0_0_Smu.bin
|
||||
PSP_SMUFW1_SUB1_FILE Typex8_0_0_1_Smu.bin
|
||||
PSP_SMUFW1_SUB2_FILE Typex8_0_0_2_Smu.bin
|
||||
PSPSECUREDEBUG_FILE Typex9_0_0_0_DbgKey.bin
|
||||
PSP_OEM_ABL_KEY_FILE Typexa_0_0_0_OemAblKey.bin
|
||||
PSP_SMUFW2_SUB0_FILE Typex12_0_0_0_Smu2.bin
|
||||
PSP_SMUFW2_SUB1_FILE Typex12_0_0_1_Smu2.bin
|
||||
PSP_SMUFW2_SUB2_FILE Typex12_0_0_2_Smu2.bin Lbb
|
||||
PSP_SEC_DEBUG_FILE Typex13_0_0_0_PspEarlyUnlock.bin Lbb
|
||||
PSP_IKEK_FILE Typex21_0_0_0_ikek.bin
|
||||
PSP_TOKEN_UNLOCK_FILE Typex22_0_0_0_PspTokenUnlockData.bin
|
||||
PSP_SECG0_FILE Typex24_0_0_0_SecureGasket.bin
|
||||
PSP_SECG1_FILE Typex24_0_0_1_SecureGasket.bin
|
||||
PSP_SECG2_FILE Typex24_0_0_2_SecureGasket.bin
|
||||
PSP_MP5FW_SUB0_FILE Typex2a_0_0_0_Mp5Fw.bin
|
||||
PSP_MP5FW_SUB1_FILE Typex2a_0_0_1_Mp5Fw.bin
|
||||
PSP_MP5FW_SUB2_FILE Typex2a_0_0_2_Mp5Fw.bin
|
||||
PSP_ABL0_FILE Typex30_0_0_0_PspAgesaBL0.bin
|
||||
SEV_CODE_FILE Typex39_0_0_0_SevCode.bin
|
||||
SEV_DATA_FILE Typex38_0_0_0_SevData.bin
|
||||
PSP_DXIOFW_FILE Typex42_0_0_0_DxioFw.bin
|
||||
UNIFIEDUSB_FILE Typex44_0_0_0_UsbPhyFw.bin
|
||||
DRTMTA_FILE Typex47_0_0_0_DrtmTa.bin
|
||||
KEYDBBL_FILE Typex50_0_0_0_PspBlPubKey.bin
|
||||
SPL_TABLE_FILE Typex55_0_0_0_BLAntiRB.bin Lbb
|
||||
PSP_MPIOFW_FILE Typex5d_0_0_0_MPIOOffchipFW.bin
|
||||
PSP_RIB_FILE_SUB0 Typex76_0_0_0_RIB.bin
|
||||
PSP_MPDMATFFW_FILE Typex8c_0_0_0_MpdmaTfFw.bin
|
||||
PSP_GMI3PHYFW_FILE Typex91_0_0_0_Gmi3PhyFw.bin
|
||||
PSP_MPDMAPMFW_FILE Typex92_0_0_0_MpdmaPmFw.bin
|
||||
AMD_FUSE_CHAIN Dummy Lbb
|
||||
|
||||
# BDT
|
||||
PSP_PMUI_FILE_SUB0_INS3 Typex64_0_3_0_PmuCode.bin
|
||||
PSP_PMUI_FILE_SUB0_INS4 Typex64_0_4_0_PmuCode.bin
|
||||
PSP_PMUI_FILE_SUB0_INS9 Typex64_0_9_0_PmuCode.bin
|
||||
PSP_PMUI_FILE_SUB0_INSA Typex64_0_a_0_PmuCode.bin
|
||||
PSP_PMUI_FILE_SUB0_INSB Typex64_0_b_0_PmuCode.bin
|
||||
PSP_PMUD_FILE_SUB0_INS3 Typex65_0_3_0_PmuData.bin
|
||||
PSP_PMUD_FILE_SUB0_INS4 Typex65_0_4_0_PmuData.bin
|
||||
PSP_PMUD_FILE_SUB0_INS9 Typex65_0_9_0_PmuData.bin
|
||||
PSP_PMUD_FILE_SUB0_INSA Typex65_0_a_0_PmuData.bin
|
||||
PSP_PMUD_FILE_SUB0_INSB Typex65_0_b_0_PmuData.bin
|
||||
PSP_PMUD_FILE_SUB0_INSC Typex65_0_c_0_PmuData.bin
|
||||
# TODO: Typex69_0_0_0_EarlyVgaImage.bin
|
||||
38
src/soc/amd/turin_poc/gpio.c
Normal file
38
src/soc/amd/turin_poc/gpio.c
Normal file
|
|
@ -0,0 +1,38 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <amdblocks/gpio.h>
|
||||
#include <gpio.h>
|
||||
#include <types.h>
|
||||
|
||||
/* see the IOMUX function table for the mapping from GPIO number to GEVENT number */
|
||||
static const struct soc_amd_event gpio_event_table[] = {
|
||||
{ GPIO_0, GEVENT_21 }, /* GPIO0 may only be used as PWR_BTN_L in ACPI */
|
||||
{ GPIO_1, GEVENT_19 },
|
||||
{ GPIO_2, GEVENT_8 },
|
||||
{ GPIO_3, GEVENT_2 },
|
||||
{ GPIO_4, GEVENT_4 },
|
||||
{ GPIO_5, GEVENT_7 },
|
||||
{ GPIO_6, GEVENT_10 },
|
||||
{ GPIO_16, GEVENT_12 },
|
||||
{ GPIO_17, GEVENT_13 },
|
||||
{ GPIO_21, GEVENT_5 },
|
||||
{ GPIO_22, GEVENT_3 },
|
||||
{ GPIO_23, GEVENT_16 },
|
||||
{ GPIO_24, GEVENT_14 },
|
||||
{ GPIO_26, GEVENT_15 },
|
||||
{ GPIO_76, GEVENT_11 },
|
||||
{ GPIO_86, GEVENT_9 },
|
||||
{ GPIO_89, GEVENT_0 },
|
||||
{ GPIO_104, GEVENT_20 },
|
||||
{ GPIO_105, GEVENT_22 },
|
||||
{ GPIO_106, GEVENT_23 },
|
||||
{ GPIO_115, GEVENT_1 },
|
||||
{ GPIO_116, GEVENT_6 },
|
||||
{ GPIO_129, GEVENT_17 },
|
||||
};
|
||||
|
||||
void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items)
|
||||
{
|
||||
*table = gpio_event_table;
|
||||
*items = ARRAY_SIZE(gpio_event_table);
|
||||
}
|
||||
57
src/soc/amd/turin_poc/i2c.c
Normal file
57
src/soc/amd/turin_poc/i2c.c
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <amdblocks/i2c.h>
|
||||
#include <soc/i2c.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <soc/southbridge.h>
|
||||
#include <static.h>
|
||||
#include "chip.h"
|
||||
|
||||
/* Table to switch SCL pins to outputs to initially reset the I2C peripherals */
|
||||
static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
|
||||
I2C_RESET_SCL_PIN(I2C0_SCL_PIN, GPIO_I2C0_SCL),
|
||||
I2C_RESET_SCL_PIN(I2C1_SCL_PIN, GPIO_I2C1_SCL),
|
||||
I2C_RESET_SCL_PIN(I2C2_SCL_PIN, GPIO_I2C2_SCL),
|
||||
I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
|
||||
I2C_RESET_SCL_PIN(I2C4_SCL_PIN, GPIO_I2C4_SCL),
|
||||
I2C_RESET_SCL_PIN(I2C5_SCL_PIN, GPIO_I2C5_SCL),
|
||||
};
|
||||
|
||||
static const struct soc_i2c_ctrlr_info i2c_ctrlr[I2C_CTRLR_COUNT] = {
|
||||
{ I2C_MASTER_MODE, APU_I2C0_BASE, "I2C0" },
|
||||
{ I2C_MASTER_MODE, APU_I2C1_BASE, "I2C1" },
|
||||
{ I2C_MASTER_MODE, APU_I2C2_BASE, "I2C2" },
|
||||
{ I2C_MASTER_MODE, APU_I2C3_BASE, "I2C3" },
|
||||
{ I2C_MASTER_MODE, APU_I2C4_BASE, "I2C4" },
|
||||
{ I2C_MASTER_MODE, APU_I2C5_BASE, "I2C5" }
|
||||
};
|
||||
|
||||
void reset_i2c_peripherals(void)
|
||||
{
|
||||
const struct soc_amd_turin_poc_config *cfg = config_of_soc();
|
||||
struct soc_i2c_peripheral_reset_info reset_info;
|
||||
|
||||
reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK;
|
||||
reset_info.i2c_scl = i2c_scl_pins;
|
||||
reset_info.num_pins = ARRAY_SIZE(i2c_scl_pins);
|
||||
sb_reset_i2c_peripherals(&reset_info);
|
||||
}
|
||||
|
||||
void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
|
||||
{
|
||||
/* TODO: write I2C pad control registers */
|
||||
}
|
||||
|
||||
const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)
|
||||
{
|
||||
*num_ctrlrs = ARRAY_SIZE(i2c_ctrlr);
|
||||
return i2c_ctrlr;
|
||||
}
|
||||
|
||||
const struct dw_i2c_bus_config *soc_get_i2c_bus_config(size_t *num_buses)
|
||||
{
|
||||
const struct soc_amd_turin_poc_config *config = config_of_soc();
|
||||
|
||||
*num_buses = ARRAY_SIZE(config->i2c);
|
||||
return config->i2c;
|
||||
}
|
||||
18
src/soc/amd/turin_poc/i3c.c
Normal file
18
src/soc/amd/turin_poc/i3c.c
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <amdblocks/i2c.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <types.h>
|
||||
|
||||
static const struct soc_i3c_ctrlr_info i3c_ctrlr[I3C_CTRLR_COUNT] = {
|
||||
{ APU_I3C0_BASE, "I3C0" },
|
||||
{ APU_I3C1_BASE, "I3C1" },
|
||||
{ APU_I3C2_BASE, "I3C2" },
|
||||
{ APU_I3C3_BASE, "I3C3" }
|
||||
};
|
||||
|
||||
const struct soc_i3c_ctrlr_info *soc_get_i3c_ctrlr_info(size_t *num_ctrlrs)
|
||||
{
|
||||
*num_ctrlrs = ARRAY_SIZE(i3c_ctrlr);
|
||||
return i3c_ctrlr;
|
||||
}
|
||||
56
src/soc/amd/turin_poc/include/soc/amd_pci_int_defs.h
Normal file
56
src/soc/amd/turin_poc/include/soc/amd_pci_int_defs.h
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef AMD_TURIN_POC_AMD_PCI_INT_DEFS_H
|
||||
#define AMD_TURIN_POC_AMD_PCI_INT_DEFS_H
|
||||
|
||||
/*
|
||||
* * PIRQ and device routing - these define the index into the
|
||||
* * FCH PCI_INTR 0xC00/0xC01 interrupt routing table.
|
||||
* */
|
||||
|
||||
#define PIRQ_NC 0x1f /* Not Used */
|
||||
#define PIRQ_A 0x00 /* INT A */
|
||||
#define PIRQ_B 0x01 /* INT B */
|
||||
#define PIRQ_C 0x02 /* INT C */
|
||||
#define PIRQ_D 0x03 /* INT D */
|
||||
#define PIRQ_E 0x04 /* INT E */
|
||||
#define PIRQ_F 0x05 /* INT F */
|
||||
#define PIRQ_G 0x06 /* INT G */
|
||||
#define PIRQ_H 0x07 /* INT H */
|
||||
#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings */
|
||||
#define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */
|
||||
#define PIRQ_HPET_L 0x0a /* Miscellaneous1 IRQ Settings */
|
||||
#define PIRQ_HPET_H 0x0b /* Miscellaneous2 IRQ Settings */
|
||||
#define PIRQ_SIRQA 0x0c /* Serial IRQ INTA */
|
||||
#define PIRQ_SIRQB 0x0d /* Serial IRQ INTB */
|
||||
#define PIRQ_SIRQC 0x0e /* Serial IRQ INTC */
|
||||
#define PIRQ_SIRQD 0x0f /* Serial IRQ INTD */
|
||||
#define PIRQ_SCI 0x10 /* SCI IRQ */
|
||||
#define PIRQ_SMBUS 0x11 /* SMBUS0 */
|
||||
#define PIRQ_ASF 0x12 /* ASF */
|
||||
/* 0x13-0x15 reserved */
|
||||
#define PIRQ_PMON 0x16 /* Performance Monitor */
|
||||
/* 0x17-0x19 reserved */
|
||||
#define PIRQ_SDIO 0x1a /* SDIO */
|
||||
/* 0x1b-0x49 reserved */
|
||||
#define PIRQ_GPP0 0x50 /* GPPInt0 */
|
||||
#define PIRQ_GPP1 0x51 /* GPPInt1 */
|
||||
#define PIRQ_GPP2 0x52 /* GPPInt2 */
|
||||
#define PIRQ_GPP3 0x53 /* GPPInt3 */
|
||||
/* 0x54-0x59 reserved */
|
||||
#define PIRQ_GSCI 0x60 /* SCI Interrupt */
|
||||
#define PIRQ_GSMI 0x61 /* SMI Interrupt */
|
||||
#define PIRQ_GPIO 0x62 /* GPIO Interrupt */
|
||||
/* 0x63-0x6f reserved */
|
||||
#define PIRQ_I2C0 0x70 /* I2C0/I3C0 */
|
||||
#define PIRQ_I2C1 0x71 /* I2C1/I3C1 */
|
||||
#define PIRQ_I2C2 0x72 /* I2C2/I3C2 */
|
||||
#define PIRQ_I2C3 0x73 /* I2C3/I3C3 */
|
||||
#define PIRQ_UART0 0x74 /* UART0 */
|
||||
#define PIRQ_UART1 0x75 /* UART1 */
|
||||
#define PIRQ_I2C4 0x76 /* I2C4 */
|
||||
#define PIRQ_I2C5 0x77 /* I2C5 */
|
||||
#define PIRQ_UART2 0x78 /* UART2 */
|
||||
#define PIRQ_UART3 0x79 /* UART3 */
|
||||
|
||||
#endif /* AMD_TURIN_POC_AMD_PCI_INT_DEFS_H */
|
||||
24
src/soc/amd/turin_poc/include/soc/aoac_defs.h
Normal file
24
src/soc/amd/turin_poc/include/soc/aoac_defs.h
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef AMD_TURIN_POC_AOAC_DEFS_H
|
||||
#define AMD_TURIN_POC_AOAC_DEFS_H
|
||||
|
||||
/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */
|
||||
#define FCH_AOAC_DEV_CLK_GEN 0
|
||||
#define FCH_AOAC_DEV_I2C0 5
|
||||
#define FCH_AOAC_DEV_I2C1 6
|
||||
#define FCH_AOAC_DEV_I2C2 7
|
||||
#define FCH_AOAC_DEV_I2C3 8
|
||||
#define FCH_AOAC_DEV_I2C4 9
|
||||
#define FCH_AOAC_DEV_I2C5 10
|
||||
#define FCH_AOAC_DEV_UART0 11
|
||||
#define FCH_AOAC_DEV_UART1 12
|
||||
#define FCH_AOAC_DEV_I3C1 13
|
||||
#define FCH_AOAC_DEV_I3C2 14
|
||||
#define FCH_AOAC_DEV_I3C3 15
|
||||
#define FCH_AOAC_DEV_UART2 16
|
||||
#define FCH_AOAC_DEV_AMBA 17
|
||||
#define FCH_AOAC_DEV_I3C0 21
|
||||
#define FCH_AOAC_DEV_ESPI 27
|
||||
|
||||
#endif /* AMD_TURIN_POC_AOAC_DEFS_H */
|
||||
9
src/soc/amd/turin_poc/include/soc/cpu.h
Normal file
9
src/soc/amd/turin_poc/include/soc/cpu.h
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef AMD_TURIN_POC_CPU_H
|
||||
#define AMD_TURIN_POC_CPU_H
|
||||
|
||||
#define TURIN_A0_CPUID CPUID_FROM_FMS(0x19, 0x10, 0)
|
||||
#define TURIN_B0_CPUID CPUID_FROM_FMS(0x19, 0x11, 0)
|
||||
|
||||
#endif /* AMD_TURIN_POC_CPU_H */
|
||||
138
src/soc/amd/turin_poc/include/soc/data_fabric.h
Normal file
138
src/soc/amd/turin_poc/include/soc/data_fabric.h
Normal file
|
|
@ -0,0 +1,138 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef AMD_TURIN_POC_DATA_FABRIC_H
|
||||
#define AMD_TURIN_POC_DATA_FABRIC_H
|
||||
|
||||
#include <amdblocks/data_fabric_defs.h>
|
||||
#include <types.h>
|
||||
|
||||
#define DF_VGA_EN DF_REG_ID(0, 0xc08)
|
||||
|
||||
union df_vga_en {
|
||||
struct {
|
||||
uint32_t ve : 1; /* [ 0.. 0] */
|
||||
uint32_t np : 1; /* [ 1.. 1] */
|
||||
uint32_t cpu_dis : 1; /* [ 2.. 2] */
|
||||
uint32_t : 1; /* [ 3.. 3] */
|
||||
uint32_t dst_fabric_id : 12; /* [ 4..15] */
|
||||
uint32_t : 16; /* [16..31] */
|
||||
};
|
||||
uint32_t raw;
|
||||
};
|
||||
|
||||
#define DF_PCI_CFG_BASE0 DF_REG_ID(0, 0xc80)
|
||||
#define DF_PCI_CFG_LIMIT0 DF_REG_ID(0, 0xc84)
|
||||
|
||||
#define DF_PCI_CFG_MAP_COUNT 8
|
||||
|
||||
#define DF_PCI_CFG_REG_OFFSET(instance) ((instance) * 2 * sizeof(uint32_t))
|
||||
#define DF_PCI_CFG_BASE(reg) (DF_PCI_CFG_BASE0 + DF_PCI_CFG_REG_OFFSET(reg))
|
||||
#define DF_PCI_CFG_LIMIT(reg) (DF_PCI_CFG_LIMIT0 + DF_PCI_CFG_REG_OFFSET(reg))
|
||||
|
||||
union df_pci_cfg_base {
|
||||
struct {
|
||||
uint32_t re : 1; /* [ 0.. 0] */
|
||||
uint32_t we : 1; /* [ 1.. 1] */
|
||||
uint32_t : 6; /* [ 2.. 7] */
|
||||
uint32_t segment_num : 8; /* [ 8..15] */
|
||||
uint32_t bus_num_base : 8; /* [16..23] */
|
||||
uint32_t : 8; /* [24..31] */
|
||||
};
|
||||
uint32_t raw;
|
||||
};
|
||||
|
||||
union df_pci_cfg_limit {
|
||||
struct {
|
||||
uint32_t dst_fabric_id : 12; /* [ 0..11] */
|
||||
uint32_t : 4; /* [12..15] */
|
||||
uint32_t bus_num_limit : 8; /* [16..23] */
|
||||
uint32_t : 8; /* [24..31] */
|
||||
};
|
||||
uint32_t raw;
|
||||
};
|
||||
|
||||
#define DF_IO_BASE0 DF_REG_ID(0, 0xd00)
|
||||
#define DF_IO_LIMIT0 DF_REG_ID(0, 0xd04)
|
||||
|
||||
#define DF_IO_REG_COUNT 8
|
||||
|
||||
#define DF_IO_REG_OFFSET(instance) ((instance) * 2 * sizeof(uint32_t))
|
||||
#define DF_IO_BASE(reg) (DF_IO_BASE0 + DF_IO_REG_OFFSET(reg))
|
||||
#define DF_IO_LIMIT(reg) (DF_IO_LIMIT0 + DF_IO_REG_OFFSET(reg))
|
||||
|
||||
union df_io_base {
|
||||
struct {
|
||||
uint32_t re : 1; /* [ 0.. 0] */
|
||||
uint32_t we : 1; /* [ 1.. 1] */
|
||||
uint32_t : 3; /* [ 2.. 4] */
|
||||
uint32_t ie : 1; /* [ 5.. 5] */
|
||||
uint32_t : 10; /* [ 6..15] */
|
||||
uint32_t io_base : 13; /* [16..28] */
|
||||
uint32_t : 3; /* [29..31] */
|
||||
};
|
||||
uint32_t raw;
|
||||
};
|
||||
|
||||
union df_io_limit {
|
||||
struct {
|
||||
uint32_t dst_fabric_id : 12; /* [ 0..11] */
|
||||
uint32_t : 4; /* [12..15] */
|
||||
uint32_t io_limit : 13; /* [16..28] */
|
||||
uint32_t : 3; /* [29..31] */
|
||||
};
|
||||
uint32_t raw;
|
||||
};
|
||||
|
||||
#define DF_IO_ADDR_SHIFT 12
|
||||
|
||||
#define DF_MMIO_BASE0 DF_REG_ID(0, 0xd80)
|
||||
#define DF_MMIO_LIMIT0 DF_REG_ID(0, 0xd84)
|
||||
#define DF_MMIO_SHIFT 16
|
||||
#define DF_MMIO_CTRL0 DF_REG_ID(0, 0xd88)
|
||||
#define DF_MMIO_ADDR_EXT0 DF_REG_ID(0, 0xd8c)
|
||||
#define DF_MMIO_EXT_ADDR_SHIFT 48
|
||||
|
||||
#define DF_MMIO_REG_SET_SIZE 4
|
||||
#define DF_MMIO_REG_SET_COUNT 16
|
||||
|
||||
union df_mmio_control {
|
||||
struct {
|
||||
uint32_t re : 1; /* [ 0.. 0] */
|
||||
uint32_t we : 1; /* [ 1.. 1] */
|
||||
uint32_t : 1; /* [ 2.. 2] */
|
||||
uint32_t np : 1; /* [ 3.. 3] */
|
||||
uint32_t : 12; /* [ 4..15] */
|
||||
uint32_t dst_fabric_id : 12; /* [16..27] */
|
||||
uint32_t : 4; /* [28..31] */
|
||||
};
|
||||
uint32_t raw;
|
||||
};
|
||||
|
||||
union df_mmio_addr_ext {
|
||||
struct {
|
||||
uint32_t base_ext : 8; /* [ 0.. 7] */
|
||||
uint32_t : 8; /* [ 8..15] */
|
||||
uint32_t limit_ext : 8; /* [16..23] */
|
||||
uint32_t : 8; /* [24..31] */
|
||||
};
|
||||
uint32_t raw;
|
||||
};
|
||||
|
||||
#define DF_FICAA_BIOS DF_REG_ID(4, 0x8C)
|
||||
#define DF_FICAD_LO DF_REG_ID(4, 0xB8)
|
||||
#define DF_FICAD_HI DF_REG_ID(4, 0xBC)
|
||||
|
||||
union df_ficaa {
|
||||
struct {
|
||||
uint32_t cfg_inst_acc_en : 1; /* [ 0.. 0] */
|
||||
uint32_t reg_num : 10; /* [10.. 1] */
|
||||
uint32_t func_num : 3; /* [13..11] */
|
||||
uint32_t b64_en : 1; /* [14..14] */
|
||||
uint32_t : 1; /* [15..15] */
|
||||
uint32_t inst_id : 8; /* [23..16] */
|
||||
uint32_t : 8; /* [31..24] */
|
||||
};
|
||||
uint32_t raw;
|
||||
};
|
||||
|
||||
#endif /* AMD_TURIN_POC_DATA_FABRIC_H */
|
||||
270
src/soc/amd/turin_poc/include/soc/gpio.h
Normal file
270
src/soc/amd/turin_poc/include/soc/gpio.h
Normal file
|
|
@ -0,0 +1,270 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef AMD_TURIN_POC_GPIO_H
|
||||
#define AMD_TURIN_POC_GPIO_H
|
||||
|
||||
#define GPIO_DEVICE_NAME "AMDI0030"
|
||||
#define GPIO_DEVICE_DESC "GPIO Controller"
|
||||
|
||||
#ifndef __ACPI__
|
||||
#include <soc/iomap.h>
|
||||
#include <amdblocks/gpio.h>
|
||||
#endif /* !__ACPI__ */
|
||||
|
||||
#include <amdblocks/gpio_defs.h>
|
||||
|
||||
/* The following sections describe only the GPIOs defined for this SOC */
|
||||
|
||||
#define SOC_GPIO_TOTAL_PINS 267
|
||||
|
||||
/* Bank 0: GPIO_0 - GPIO_63 */
|
||||
#define GPIO_0 0
|
||||
#define GPIO_1 1
|
||||
#define GPIO_2 2
|
||||
#define GPIO_3 3
|
||||
#define GPIO_4 4
|
||||
#define GPIO_5 5
|
||||
#define GPIO_6 6
|
||||
#define GPIO_7 7
|
||||
#define GPIO_12 12
|
||||
#define GPIO_13 13
|
||||
#define GPIO_14 14
|
||||
#define GPIO_16 16
|
||||
#define GPIO_17 17
|
||||
#define GPIO_19 19
|
||||
#define GPIO_20 20
|
||||
#define GPIO_21 21
|
||||
#define GPIO_22 22
|
||||
#define GPIO_23 23
|
||||
#define GPIO_24 24
|
||||
#define GPIO_26 26
|
||||
|
||||
/* Bank 1: GPIO_64 - GPIO_127 */
|
||||
#define GPIO_74 74
|
||||
#define GPIO_75 75
|
||||
#define GPIO_76 76
|
||||
#define GPIO_86 86
|
||||
#define GPIO_87 87
|
||||
#define GPIO_88 88
|
||||
#define GPIO_89 89
|
||||
#define GPIO_104 104
|
||||
#define GPIO_105 105
|
||||
#define GPIO_106 106
|
||||
#define GPIO_107 107
|
||||
#define GPIO_108 108
|
||||
#define GPIO_109 109
|
||||
#define GPIO_110 110
|
||||
#define GPIO_115 115
|
||||
#define GPIO_116 116
|
||||
#define GPIO_117 117
|
||||
#define GPIO_118 118
|
||||
#define GPIO_119 119
|
||||
#define GPIO_120 120
|
||||
#define GPIO_121 121
|
||||
#define GPIO_122 122
|
||||
#define GPIO_123 123
|
||||
#define GPIO_124 124
|
||||
#define GPIO_125 125
|
||||
#define GPIO_126 126
|
||||
|
||||
/* Bank 2: GPIO_128 - GPIO_191 */
|
||||
#define GPIO_129 129
|
||||
#define GPIO_131 131
|
||||
#define GPIO_132 132
|
||||
#define GPIO_133 133
|
||||
#define GPIO_134 134
|
||||
#define GPIO_135 135
|
||||
#define GPIO_136 136
|
||||
#define GPIO_137 137
|
||||
#define GPIO_138 138
|
||||
#define GPIO_139 139
|
||||
#define GPIO_141 141
|
||||
#define GPIO_142 142
|
||||
#define GPIO_145 145
|
||||
#define GPIO_146 146
|
||||
#define GPIO_147 147
|
||||
#define GPIO_148 148
|
||||
#define GPIO_149 149
|
||||
#define GPIO_150 150
|
||||
#define GPIO_151 151
|
||||
#define GPIO_152 152
|
||||
|
||||
/* remote GPIO bank: GPIO_256 - GPIO_271 */
|
||||
#define GPIO_256 256
|
||||
#define GPIO_257 257
|
||||
#define GPIO_258 258
|
||||
#define GPIO_259 259
|
||||
#define GPIO_260 260
|
||||
#define GPIO_261 261
|
||||
#define GPIO_262 262
|
||||
#define GPIO_263 263
|
||||
#define GPIO_264 264
|
||||
#define GPIO_265 265
|
||||
#define GPIO_266 266
|
||||
|
||||
/* IOMUX function names and values */
|
||||
#define GPIO_0_IOMUX_PWR_BTN_L 0
|
||||
#define GPIO_0_IOMUX_GPIO_PU1PD0 1
|
||||
#define GPIO_0_IOMUX_GPIOxx 2
|
||||
#define GPIO_1_IOMUX_SYS_RESET_L 0
|
||||
#define GPIO_1_IOMUX_GPIOxx 1
|
||||
#define GPIO_2_IOMUX_WAKE_L 0
|
||||
#define GPIO_2_IOMUX_GPIOxx 1
|
||||
#define GPIO_3_IOMUX_GPIOxx 0
|
||||
#define GPIO_4_IOMUX_GPIOxx 0
|
||||
#define GPIO_4_IOMUX_SATA_ACT_L 1
|
||||
#define GPIO_5_IOMUX_GPIOxx 0
|
||||
#define GPIO_5_IOMUX_DEVSLP0 1
|
||||
#define GPIO_6_IOMUX_GPIOxx 0
|
||||
#define GPIO_6_IOMUX_DEVSLP1 1
|
||||
#define GPIO_7_IOMUX_GPIOxx 0
|
||||
#define GPIO_12_IOMUX_PWRGD_OUT 0
|
||||
#define GPIO_12_IOMUX_GPIOxx 1
|
||||
#define GPIO_13_IOMUX_I2C4_SCL 0
|
||||
#define GPIO_13_IOMUX_CLK_48_24_0 1
|
||||
#define GPIO_13_IOMUX_GPIOxx 2
|
||||
#define GPIO_14_IOMUX_I2C4_SDA 0
|
||||
#define GPIO_14_IOMUX_S0A3 1
|
||||
#define GPIO_14_IOMUX_GPIOxx 2
|
||||
#define GPIO_16_IOMUX_USB_1O_OC_L 0
|
||||
#define GPIO_16_IOMUX_GPIOxx 1
|
||||
#define GPIO_17_IOMUX_USB11_OC_L 0
|
||||
#define GPIO_17_IOMUX_GPIOxx 1
|
||||
#define GPIO_19_IOMUX_I2C5_SCL 0
|
||||
#define GPIO_19_IOMUX_SMBUS1_SCL 1
|
||||
#define GPIO_19_IOMUX_GPIOxx 2
|
||||
#define GPIO_20_IOMUX_I2C5_SDA 0
|
||||
#define GPIO_20_IOMUX_SMBUS1_SDA 1
|
||||
#define GPIO_20_IOMUX_GPIOxx 2
|
||||
#define GPIO_21_IOMUX_GPIOxx 0
|
||||
#define GPIO_22_IOMUX_GPIOxx 0
|
||||
#define GPIO_23_IOMUX_ESPI_RST_OUT_L 0
|
||||
#define GPIO_23_IOMUX_GPIOxx 1
|
||||
#define GPIO_24_IOMUX_SMERR_L 0
|
||||
#define GPIO_24_IOMUX_GPIOxx 1
|
||||
#define GPIO_26_IOMUX_PCIE_RST1_L 0
|
||||
#define GPIO_26_IOMUX_GPIOxx 1
|
||||
#define GPIO_74_IOMUX_ESPI_CLK2 0
|
||||
#define GPIO_74_IOMUX_GPIOxx 1
|
||||
#define GPIO_75_IOMUX_ESPI_CLK1 0
|
||||
#define GPIO_75_IOMUX_GPIOxx 1
|
||||
#define GPIO_76_IOMUX_GPIOxx 0
|
||||
#define GPIO_76_IOMUX_SPI_TPM_CS_L 1
|
||||
#define GPIO_86_IOMUX_NMI_SYNC_FLOOD_L 0
|
||||
#define GPIO_87_IOMUX_GPIOxx 0
|
||||
#define GPIO_88_IOMUX_GPIOxx 0
|
||||
#define GPIO_89_IOMUX_GENINT_L 0
|
||||
#define GPIO_89_IOMUX_PM_INTR_L 1
|
||||
#define GPIO_89_IOMUX_GPIOxx 2
|
||||
#define GPIO_104_IOMUX_GPIOxx 0
|
||||
#define GPIO_105_IOMUX_GPIOxx 0
|
||||
#define GPIO_106_IOMUX_GPIOxx 0
|
||||
#define GPIO_107_IOMUX_GPIOxx 0
|
||||
#define GPIO_108_IOMUX_ESPI0_ALERT_D1 0
|
||||
#define GPIO_108_IOMUX_GPIOxx 1
|
||||
#define GPIO_109_IOMUX_GPIOxx 0
|
||||
#define GPIO_110_IOMUX_ESPI1_ALERT_D1 0
|
||||
#define GPIO_110_IOMUX_GPIOxx 1
|
||||
#define GPIO_115_IOMUX_GPIOxx 0
|
||||
#define GPIO_115_IOMUX_CLK_REQ11_L 1
|
||||
#define GPIO_116_IOMUX_GPIOxx 0
|
||||
#define GPIO_116_IOMUX_CLK_REQ12_L 1
|
||||
#define GPIO_117_IOMUX_ESPI_CLK0 0
|
||||
#define GPIO_117_IOMUX_GPIOxx 1
|
||||
#define GPIO_118_IOMUX_SPI_CS0_L 0
|
||||
#define GPIO_118_IOMUX_GPIOxx 1
|
||||
#define GPIO_119_IOMUX_SPI_CS1_L 0
|
||||
#define GPIO_119_IOMUX_GPIOxx 1
|
||||
#define GPIO_120_IOMUX_ESPI0_DATA0 0
|
||||
#define GPIO_120_IOMUX_GPIOxx 1
|
||||
#define GPIO_121_IOMUX_ESPI0_DATA1 0
|
||||
#define GPIO_121_IOMUX_GPIOxx 1
|
||||
#define GPIO_122_IOMUX_ESPI0_DATA2 0
|
||||
#define GPIO_122_IOMUX_GPIOxx 1
|
||||
#define GPIO_123_IOMUX_ESPI0_DATA3 0
|
||||
#define GPIO_123_IOMUX_GPIOxx 1
|
||||
#define GPIO_124_IOMUX_ESPI_CS0_L 0
|
||||
#define GPIO_124_IOMUX_GPIOxx 1
|
||||
#define GPIO_125_IOMUX_ESPI_CS1_L 0
|
||||
#define GPIO_125_IOMUX_GPIOxx 1
|
||||
#define GPIO_126_IOMUX_SPI_CS2_L 0
|
||||
#define GPIO_126_IOMUX_GPIOxx 1
|
||||
#define GPIO_129_IOMUX_ESPI_RSTIN_L 0
|
||||
#define GPIO_129_IOMUX_KBRST_L 1
|
||||
#define GPIO_129_IOMUX_GPIOxx 2
|
||||
#define GPIO_131_IOMUX_ESPI1_DATA0 0
|
||||
#define GPIO_131_IOMUX_GPIOxx 1
|
||||
#define GPIO_132_IOMUX_ESPI1_DATA1 0
|
||||
#define GPIO_132_IOMUX_GPIOxx 1
|
||||
#define GPIO_133_IOMUX_ESPI1_DATA2 0
|
||||
#define GPIO_133_IOMUX_GPIOxx 1
|
||||
#define GPIO_134_IOMUX_ESPI1_DATA3 0
|
||||
#define GPIO_134_IOMUX_GPIOxx 1
|
||||
#define GPIO_135_IOMUX_UART0_CTS_L 0
|
||||
#define GPIO_135_IOMUX_UART2_TXD 1
|
||||
#define GPIO_135_IOMUX_GPIOxx 2
|
||||
#define GPIO_136_IOMUX_UART0_RXD 0
|
||||
#define GPIO_136_IOMUX_GPIOxx 1
|
||||
#define GPIO_137_IOMUX_UART0_RTS_L 0
|
||||
#define GPIO_137_IOMUX_UART2_RXD 1
|
||||
#define GPIO_137_IOMUX_GPIOxx 2
|
||||
#define GPIO_138_IOMUX_UART0_TXD 0
|
||||
#define GPIO_138_IOMUX_GPIOxx 1
|
||||
#define GPIO_139_IOMUX_UART0_INTR 0
|
||||
#define GPIO_139_IOMUX_GPIOxx 1
|
||||
#define GPIO_141_IOMUX_UART1_RXD 0
|
||||
#define GPIO_141_IOMUX_GPIOxx 1
|
||||
#define GPIO_142_IOMUX_UART1_TXD 0
|
||||
#define GPIO_142_IOMUX_GPIOxx 1
|
||||
#define GPIO_145_IOMUX_I3C0_SCL_SPD0_SCL 0
|
||||
#define GPIO_145_IOMUX_I2C0_SCL_SPD0_SCL 1
|
||||
#define GPIO_145_IOMUX_SMBUS0_SCL 2
|
||||
#define GPIO_145_IOMUX_GPIOxx 3
|
||||
#define GPIO_146_IOMUX_I3C0_SDA_SPD0_SDA 0
|
||||
#define GPIO_146_IOMUX_I2C0_SDA_SPD0_SDA 1
|
||||
#define GPIO_146_IOMUX_SMBUS0_SDA 2
|
||||
#define GPIO_146_IOMUX_GPIOxx 3
|
||||
#define GPIO_147_IOMUX_I3C1_SCL_SPD1_SCL 0
|
||||
#define GPIO_147_IOMUX_I2C1_SCL_SPD1_SCL 1
|
||||
#define GPIO_147_IOMUX_GPIOxx 2
|
||||
#define GPIO_148_IOMUX_I3C1_SDA_SPD1_SDA 0
|
||||
#define GPIO_148_IOMUX_I2C1_SDA_SPD1_SDA 1
|
||||
#define GPIO_148_IOMUX_GPIOxx 2
|
||||
#define GPIO_149_IOMUX_I3C2_SCL_SPD2_SCL 0
|
||||
#define GPIO_149_IOMUX_I2C2_SCL_SPD2_SCL 1
|
||||
#define GPIO_149_IOMUX_GPIOxx 2
|
||||
#define GPIO_150_IOMUX_I3C2_SDA_SPD2_SDA 0
|
||||
#define GPIO_150_IOMUX_I2C2_SDA_SPD2_SDA 1
|
||||
#define GPIO_150_IOMUX_GPIOxx 2
|
||||
#define GPIO_151_IOMUX_I3C3_SCL_SPD3_SCL 0
|
||||
#define GPIO_151_IOMUX_I2C3_SCL_SPD3_SCL 1
|
||||
#define GPIO_151_IOMUX_GPIOxx 2
|
||||
#define GPIO_152_IOMUX_I3C3_SDA_SPD3_SDA 0
|
||||
#define GPIO_152_IOMUX_I2C3_SDA_SPD3_SDA 1
|
||||
#define GPIO_152_IOMUX_GPIOxx 2
|
||||
|
||||
/* Remote GPIOs */
|
||||
#define GPIO_256_IOMUX_GPIOxx 0
|
||||
#define GPIO_256_IOMUX_SGPIO0_CLK 1
|
||||
#define GPIO_257_IOMUX_GPIOxx 0
|
||||
#define GPIO_257_IOMUX_SGPIO1_CLK 1
|
||||
#define GPIO_257_IOMUX_CLK_REQ01_L 2
|
||||
#define GPIO_258_IOMUX_GPIOxx 0
|
||||
#define GPIO_258_IOMUX_SGPIO2_CLK 1
|
||||
#define GPIO_258_IOMUX_CLK_REQ02_L 2
|
||||
#define GPIO_259_IOMUX_GPIOxx 0
|
||||
#define GPIO_259_IOMUX_SGPIO3_CLK 1
|
||||
#define GPIO_260_IOMUX_SGPIO_DATAOUT 0
|
||||
#define GPIO_260_IOMUX_GPIOxx 1
|
||||
#define GPIO_261_IOMUX_SGPIO_LOAD 0
|
||||
#define GPIO_261_IOMUX_GPIOxx 1
|
||||
#define GPIO_262_IOMUX_GPIOxx 0
|
||||
#define GPIO_263_IOMUX_GPIOxx 0
|
||||
#define GPIO_264_IOMUX_USB00_OC_L 0
|
||||
#define GPIO_264_IOMUX_GPIOxx 1
|
||||
#define GPIO_265_IOMUX_USB01_OC_L 0
|
||||
#define GPIO_265_IOMUX_GPIOxx 1
|
||||
#define GPIO_266_IOMUX_PCIE_RST0_L 0
|
||||
#define GPIO_266_IOMUX_GPIOxx 1
|
||||
|
||||
#endif /* AMD_TURIN_POC_GPIO_H */
|
||||
36
src/soc/amd/turin_poc/include/soc/i2c.h
Normal file
36
src/soc/amd/turin_poc/include/soc/i2c.h
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef AMD_TURIN_POC_I2C_H
|
||||
#define AMD_TURIN_POC_I2C_H
|
||||
|
||||
#include <gpio.h>
|
||||
#include <types.h>
|
||||
|
||||
#define GPIO_I2C0_SCL BIT(0)
|
||||
#define GPIO_I2C1_SCL BIT(1)
|
||||
#define GPIO_I2C2_SCL BIT(2)
|
||||
#define GPIO_I2C3_SCL BIT(3)
|
||||
#define GPIO_I2C4_SCL BIT(4)
|
||||
#define GPIO_I2C5_SCL BIT(5)
|
||||
#define GPIO_I2C_MASK (GPIO_I2C0_SCL | GPIO_I2C1_SCL | \
|
||||
GPIO_I2C2_SCL | GPIO_I2C3_SCL | \
|
||||
GPIO_I2C4_SCL | GPIO_I2C5_SCL)
|
||||
|
||||
|
||||
#define I2C0_SCL_PIN GPIO_145
|
||||
#define I2C1_SCL_PIN GPIO_147
|
||||
#define I2C2_SCL_PIN GPIO_149
|
||||
#define I2C3_SCL_PIN GPIO_151
|
||||
#define I2C4_SCL_PIN GPIO_13
|
||||
#define I2C5_SCL_PIN GPIO_19
|
||||
|
||||
#define I2C0_SCL_PIN_IOMUX_GPIOxx GPIO_145_IOMUX_GPIOxx
|
||||
#define I2C1_SCL_PIN_IOMUX_GPIOxx GPIO_147_IOMUX_GPIOxx
|
||||
#define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_149_IOMUX_GPIOxx
|
||||
#define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_151_IOMUX_GPIOxx
|
||||
#define I2C4_SCL_PIN_IOMUX_GPIOxx GPIO_13_IOMUX_GPIOxx
|
||||
#define I2C5_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx
|
||||
|
||||
void reset_i2c_peripherals(void);
|
||||
|
||||
#endif /* AMD_TURIN_POC_I2C_H */
|
||||
38
src/soc/amd/turin_poc/include/soc/iomap.h
Normal file
38
src/soc/amd/turin_poc/include/soc/iomap.h
Normal file
|
|
@ -0,0 +1,38 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef AMD_TURIN_POC_IOMAP_H
|
||||
#define AMD_TURIN_POC_IOMAP_H
|
||||
|
||||
#define I2C_MASTER_DEV_COUNT 6
|
||||
#define I2C_PERIPHERAL_DEV_COUNT 0
|
||||
#define I2C_CTRLR_COUNT (I2C_MASTER_DEV_COUNT + I2C_PERIPHERAL_DEV_COUNT)
|
||||
#define I3C_CTRLR_COUNT 4
|
||||
|
||||
#define SPI_BASE_ADDRESS 0xfec10000
|
||||
|
||||
/* @Todo : Check these values for Turin */
|
||||
|
||||
/* I/O Ranges */
|
||||
#define ACPI_IO_BASE 0x0400
|
||||
#define ACPI_CSTATE_CONTROL (ACPI_IO_BASE + 0x10)
|
||||
|
||||
/* FCH AL2AHB Registers */
|
||||
#define ALINK_AHB_ADDRESS 0xfedc0000
|
||||
|
||||
#define APU_I2C0_BASE 0xfedc2000
|
||||
#define APU_I2C1_BASE 0xfedc3000
|
||||
#define APU_I2C2_BASE 0xfedc4000
|
||||
#define APU_I2C3_BASE 0xfedc5000
|
||||
#define APU_I2C4_BASE 0xfedc6000
|
||||
#define APU_I2C5_BASE 0xfedcb000
|
||||
|
||||
#define APU_UART0_BASE 0xfedc9000
|
||||
#define APU_UART1_BASE 0xfedca000
|
||||
#define APU_UART2_BASE 0xfedce000
|
||||
|
||||
#define APU_I3C0_BASE 0xfedd2000
|
||||
#define APU_I3C1_BASE 0xfedd3000
|
||||
#define APU_I3C2_BASE 0xfedd4000
|
||||
#define APU_I3C3_BASE 0xfedd6000
|
||||
|
||||
#endif /* AMD_TURIN_POC_IOMAP_H */
|
||||
16
src/soc/amd/turin_poc/include/soc/lpc.h
Normal file
16
src/soc/amd/turin_poc/include/soc/lpc.h
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef AMD_TURIN_POC_LPC_H
|
||||
#define AMD_TURIN_POC_LPC_H
|
||||
|
||||
#define SPI_BASE_ADDRESS_REGISTER 0xa0
|
||||
#define SPI_BASE_ALIGNMENT BIT(8)
|
||||
#define SPI_BASE_RESERVED (BIT(5) | BIT(6) | BIT(7))
|
||||
#define PSP_SPI_MMIO_SEL BIT(4)
|
||||
#define ROUTE_TPM_2_SPI BIT(3)
|
||||
#define SPI_ABORT_ENABLE BIT(2)
|
||||
#define SPI_ROM_ENABLE BIT(1)
|
||||
#define SPI_ROM_ALT_ENABLE BIT(0)
|
||||
#define SPI_PRESERVE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4))
|
||||
|
||||
#endif /* AMD_TURIN_POC_LPC_H */
|
||||
23
src/soc/amd/turin_poc/include/soc/msr.h
Normal file
23
src/soc/amd/turin_poc/include/soc/msr.h
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef AMD_TURIN_POC_MSR_H
|
||||
#define AMD_TURIN_POC_MSR_H
|
||||
|
||||
#include <cpu/amd/msr.h>
|
||||
|
||||
/* MSRC001_00[6B:64] P-state [7:0] bit definitions */
|
||||
union pstate_msr {
|
||||
struct {
|
||||
uint64_t cpu_fid_0_7 : 8; /* [ 0.. 7] */
|
||||
uint64_t cpu_dfs_id : 6; /* [ 8..13] */
|
||||
uint64_t cpu_vid_0_7 : 8; /* [14..21] */
|
||||
uint64_t idd_value : 8; /* [22..29] */
|
||||
uint64_t idd_div : 2; /* [30..31] */
|
||||
uint64_t cpu_vid_8 : 1; /* [32..32] */
|
||||
uint64_t : 30; /* [33..62] */
|
||||
uint64_t pstate_en : 1; /* [63..63] */
|
||||
};
|
||||
uint64_t raw;
|
||||
};
|
||||
|
||||
#endif /* AMD_TURIN_POC_MSR_H */
|
||||
22
src/soc/amd/turin_poc/include/soc/nvs.h
Normal file
22
src/soc/amd/turin_poc/include/soc/nvs.h
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
/* TODO: Check if this is still correct */
|
||||
|
||||
/*
|
||||
* NOTE: The layout of the global_nvs structure below must match the layout
|
||||
* in soc/soc/amd/turin_poc/acpi/globalnvs.asl !!!
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef AMD_TURIN_POC_NVS_H
|
||||
#define AMD_TURIN_POC_NVS_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
struct __packed global_nvs {
|
||||
/* Miscellaneous */
|
||||
uint64_t pm1i; /* 0x00 - 0x07 - System Wake Source - PM1 Index */
|
||||
uint64_t gpei; /* 0x08 - 0x0f - GPE Wake Source */
|
||||
};
|
||||
|
||||
#endif /* AMD_TURIN_POC_NVS_H */
|
||||
54
src/soc/amd/turin_poc/include/soc/pci_devs.h
Normal file
54
src/soc/amd/turin_poc/include/soc/pci_devs.h
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef AMD_TURIN_POC_PCI_DEVS_H
|
||||
#define AMD_TURIN_POC_PCI_DEVS_H
|
||||
|
||||
#include <device/pci_def.h>
|
||||
#include <amdblocks/pci_devs.h>
|
||||
|
||||
/* GNB Root Complex */
|
||||
#define GNB_DEV 0x0
|
||||
#define GNB_FUNC 0
|
||||
#define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC)
|
||||
#define SOC_GNB_DEV _SOC_DEV(GNB_DEV, GNB_FUNC)
|
||||
|
||||
/* SMBUS */
|
||||
#define SMBUS_DEV 0x14
|
||||
#define SMBUS_FUNC 0
|
||||
#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)
|
||||
#define SOC_SMBUS_DEV _SOC_DEV(SMBUS_DEV, SMBUS_FUNC)
|
||||
|
||||
/* LPC BUS */
|
||||
#define PCU_DEV 0x14
|
||||
#define LPC_FUNC 3
|
||||
#define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC)
|
||||
#define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC)
|
||||
|
||||
/* Data Fabric functions */
|
||||
#define DF_DEV 0x18
|
||||
|
||||
#define DF_F0_DEVFN PCI_DEVFN(DF_DEV, 0)
|
||||
#define SOC_DF_F0_DEV _SOC_DEV(DF_DEV, 0)
|
||||
|
||||
#define DF_F1_DEVFN PCI_DEVFN(DF_DEV, 1)
|
||||
#define SOC_DF_F1_DEV _SOC_DEV(DF_DEV, 1)
|
||||
|
||||
#define DF_F2_DEVFN PCI_DEVFN(DF_DEV, 2)
|
||||
#define SOC_DF_F2_DEV _SOC_DEV(DF_DEV, 2)
|
||||
|
||||
#define DF_F3_DEVFN PCI_DEVFN(DF_DEV, 3)
|
||||
#define SOC_DF_F3_DEV _SOC_DEV(DF_DEV, 3)
|
||||
|
||||
#define DF_F4_DEVFN PCI_DEVFN(DF_DEV, 4)
|
||||
#define SOC_DF_F4_DEV _SOC_DEV(DF_DEV, 4)
|
||||
|
||||
#define DF_F5_DEVFN PCI_DEVFN(DF_DEV, 5)
|
||||
#define SOC_DF_F5_DEV _SOC_DEV(DF_DEV, 5)
|
||||
|
||||
#define DF_F6_DEVFN PCI_DEVFN(DF_DEV, 6)
|
||||
#define SOC_DF_F6_DEV _SOC_DEV(DF_DEV, 6)
|
||||
|
||||
#define DF_F7_DEVFN PCI_DEVFN(DF_DEV, 7)
|
||||
#define SOC_DF_F7_DEV _SOC_DEV(DF_DEV, 7)
|
||||
|
||||
#endif /* AMD_TURIN_POC_PCI_DEVS_H */
|
||||
182
src/soc/amd/turin_poc/include/soc/smi.h
Normal file
182
src/soc/amd/turin_poc/include/soc/smi.h
Normal file
|
|
@ -0,0 +1,182 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#ifndef AMD_TURIN_POC_SMI_H
|
||||
#define AMD_TURIN_POC_SMI_H
|
||||
|
||||
#include <types.h>
|
||||
|
||||
#define SMI_GEVENTS 24
|
||||
#define SCIMAPS 64 /* 0..63 */
|
||||
#define SCI_GPES 32
|
||||
#define NUMBER_SMITYPES 157
|
||||
|
||||
#define SMI_EVENT_STATUS 0x0
|
||||
#define SMI_EVENT_ENABLE 0x04
|
||||
#define SMI_SCI_TRIG 0x08
|
||||
#define SMI_SCI_LEVEL 0x0c
|
||||
#define SMI_SCI_STATUS 0x10
|
||||
#define SMI_SCI_EN 0x14
|
||||
#define SMI_SCI_MAP0 0x40
|
||||
# define SMI_SCI_MAP(X) (SMI_SCI_MAP0 + (X))
|
||||
|
||||
/* SMI source and status */
|
||||
#define SMITYPE_G_GENINT1_L 0
|
||||
#define SMITYPE_G_AGPIO115 1
|
||||
#define SMITYPE_G_AGPIO3 2
|
||||
#define SMITYPE_G_AGPIO22 3
|
||||
#define SMITYPE_G_AGPIO4 4
|
||||
#define SMITYPE_G_AGPIO21 5
|
||||
#define SMITYPE_G_AGPIO116 6
|
||||
#define SMITYPE_G_AGPIO5 7
|
||||
#define SMITYPE_G_WAKE_L 8
|
||||
#define SMITYPE_G_NMI_SYNC_FLOOD 9
|
||||
#define SMITYPE_G_AGPIO6 10
|
||||
#define SMITYPE_G_AGPIO76 11
|
||||
#define SMITYPE_G_USBOC0_L 12
|
||||
#define SMITYPE_G_USBOC1_L 13
|
||||
#define SMITYPE_G_SMERR_L 14
|
||||
#define SMITYPE_G_PCIE_RST1_L 15
|
||||
#define SMITYPE_G_ESPI_RSTOUT_L 16
|
||||
#define SMITYPE_G_ESPI_RSTIN_L 17
|
||||
#define SMITYPE_G_X48M_OUT 18
|
||||
#define SMITYPE_G_SYSRESET_L 19
|
||||
#define SMITYPE_G_AGPIO104 20
|
||||
#define SMITYPE_G_PWR_BTN_L 21
|
||||
#define SMITYPE_G_AGPI105 22
|
||||
#define SMITYPE_G_AGPI106 23
|
||||
#define GEVENT_MASK ((1 << SMITYPE_G_GENINT1_L) \
|
||||
| (1 << SMITYPE_G_AGPIO115) \
|
||||
| (1 << SMITYPE_G_AGPIO3) \
|
||||
| (1 << SMITYPE_G_AGPIO22) \
|
||||
| (1 << SMITYPE_G_AGPIO4) \
|
||||
| (1 << SMITYPE_G_AGPIO21) \
|
||||
| (1 << SMITYPE_G_AGPIO116) \
|
||||
| (1 << SMITYPE_G_AGPIO5) \
|
||||
| (1 << SMITYPE_G_WAKE_L) \
|
||||
| (1 << SMITYPE_G_NMI_SYNC_FLOOD) \
|
||||
| (1 << SMITYPE_G_AGPIO6) \
|
||||
| (1 << SMITYPE_G_AGPIO76) \
|
||||
| (1 << SMITYPE_G_USBOC0_L) \
|
||||
| (1 << SMITYPE_G_USBOC1_L) \
|
||||
| (1 << SMITYPE_G_SMERR_L) \
|
||||
| (1 << SMITYPE_G_PCIE_RST1_L) \
|
||||
| (1 << SMITYPE_G_ESPI_RSTOUT_L) \
|
||||
| (1 << SMITYPE_G_ESPI_RSTIN_L) \
|
||||
| (1 << SMITYPE_G_X48M_OUT) \
|
||||
| (1 << SMITYPE_G_SYSRESET_L) \
|
||||
| (1 << SMITYPE_G_AGPIO104) \
|
||||
| (1 << SMITYPE_G_PWR_BTN_L) \
|
||||
| (1 << SMITYPE_G_AGPI105) \
|
||||
| (1 << SMITYPE_G_AGPI106))
|
||||
#define SMITYPE_MP2_WAKE 24
|
||||
#define SMITYPE_MP2_GPIO0 25
|
||||
#define SMITYPE_ESPI_SYS 26
|
||||
#define SMITYPE_ESPI_WAKE_PME 27
|
||||
#define SMITYPE_MP2_GPIO1 28
|
||||
#define SMITYPE_GPP_PME 29
|
||||
#define SMITYPE_NB_GPP_HOT_PLUG 30
|
||||
/* 31 Reserved */
|
||||
#define SMITYPE_WAKE_L2 32
|
||||
#define SMITYPE_PSP 33
|
||||
/* 34-35 Reserved */
|
||||
#define SMITYPE_ESPI_SCI_B 36
|
||||
#define SMITYPE_ESPI1_SYS_EVT_B 37
|
||||
#define SMITYPE_ESPI1_WAKE_PME 38
|
||||
#define SMITYPE_AZPME 39
|
||||
#define SMITYPE_USB_PD_I2C4 40
|
||||
#define SMITYPE_GPIO_CTL 41
|
||||
#define SMITYPE_ESPI1_SCI_B 42
|
||||
#define SMITYPE_ALT_HPET_ALARM 43
|
||||
#define SMITYPE_FAN_THERMAL 44
|
||||
#define SMITYPE_ASF_MASTER_SLAVE 45
|
||||
#define SMITYPE_I2S_WAKE 46
|
||||
#define SMITYPE_SMBUS0_MASTER 47
|
||||
#define SMITYPE_TWARN 48
|
||||
#define SMITYPE_TRAFFIC_MON 49
|
||||
#define SMITYPE_ILLB 50
|
||||
#define SMITYPE_PWRBUTTON_UP 51
|
||||
#define SMITYPE_PROCHOT 52
|
||||
#define SMITYPE_APU_HW 53
|
||||
#define SMITYPE_NB_SCI 54
|
||||
#define SMITYPE_RAS_SERR 55
|
||||
#define SMITYPE_XHC0_PME 56
|
||||
#define SMITYPE_XHC1_PME 57
|
||||
#define SMITYPE_ACDC_TIMER 58
|
||||
/* 59-63 Reserved */
|
||||
#define SMITYPE_KB_RESET 64
|
||||
#define SMITYPE_SLP_TYP 65
|
||||
#define SMITYPE_AL2H_ACPI 66
|
||||
/* 67-71 Reserved */
|
||||
#define SMITYPE_GBL_RLS 72
|
||||
#define SMITYPE_BIOS_RLS 73
|
||||
#define SMITYPE_PWRBUTTON_DOWN 74
|
||||
#define SMITYPE_SMI_CMD_PORT 75
|
||||
#define SMITYPE_USB_SMI 76
|
||||
#define SMITYPE_SERIRQ 77
|
||||
#define SMITYPE_SMBUS0_INTR 78
|
||||
/* 79-80 Reserved */
|
||||
#define SMITYPE_INTRUDER 81
|
||||
#define SMITYPE_VBAT_LOW 82
|
||||
#define SMITYPE_PROTHOT 83
|
||||
#define SMITYPE_PCI_SERR 84
|
||||
/* 85-89 Reserved */
|
||||
#define SMITYPE_EMUL60_64 90
|
||||
/* 91-132 Reserved */
|
||||
#define SMITYPE_FANIN0 133
|
||||
/* 134-140 Reserved */
|
||||
#define SMITYPE_CF9_WRITE 141
|
||||
#define SMITYPE_SHORT_TIMER 142
|
||||
#define SMITYPE_LONG_TIMER 143
|
||||
#define SMITYPE_AB_SMI 144
|
||||
/* 145 Reserved */
|
||||
#define SMITYPE_ESPI_SMI 146
|
||||
#define SMITYPE_ESPI1_SMI 147
|
||||
#define SMITYPE_IOTRAP0 148
|
||||
#define SMITYPE_IOTRAP1 149
|
||||
#define SMITYPE_IOTRAP2 150
|
||||
#define SMITYPE_IOTRAP3 151
|
||||
#define SMITYPE_MEMTRAP0 152
|
||||
/* 153-155 Reserved */
|
||||
#define SMITYPE_CFGTRAP0 156
|
||||
/* 157-159 Reserved */
|
||||
|
||||
#define TYPE_TO_MASK(X) (1 << (X) % 32)
|
||||
|
||||
#define SMI_REG_SMISTS0 0x80
|
||||
#define SMI_REG_SMISTS1 0x84
|
||||
#define SMI_REG_SMISTS2 0x88
|
||||
#define SMI_REG_SMISTS3 0x8c
|
||||
#define SMI_REG_SMISTS4 0x90
|
||||
|
||||
#define SMI_REG_POINTER 0x94
|
||||
# define SMI_STATUS_SRC_SCI (1 << 0)
|
||||
# define SMI_STATUS_SRC_0 (1 << 1) /* SMIx80 */
|
||||
# define SMI_STATUS_SRC_1 (1 << 2) /* SMIx84... */
|
||||
# define SMI_STATUS_SRC_2 (1 << 3)
|
||||
# define SMI_STATUS_SRC_3 (1 << 4)
|
||||
# define SMI_STATUS_SRC_4 (1 << 5)
|
||||
|
||||
#define SMI_TIMER 0x96
|
||||
#define SMI_TIMER_MASK 0x7fff
|
||||
#define SMI_TIMER_EN (1 << 15)
|
||||
|
||||
#define SMI_REG_SMITRIG0 0x98
|
||||
# define SMITRIG0_PSP (1 << 25)
|
||||
# define SMITRG0_EOS (1 << 28)
|
||||
# define SMI_TIMER_SEL (1 << 29)
|
||||
# define SMITRG0_SMIENB (1 << 31)
|
||||
|
||||
#define SMI_REG_CONTROL0 0xa0
|
||||
#define SMI_REG_CONTROL1 0xa4
|
||||
#define SMI_REG_CONTROL2 0xa8
|
||||
#define SMI_REG_CONTROL3 0xac
|
||||
#define SMI_REG_CONTROL4 0xb0
|
||||
#define SMI_REG_CONTROL5 0xb4
|
||||
#define SMI_REG_CONTROL6 0xb8
|
||||
#define SMI_REG_CONTROL7 0xbc
|
||||
#define SMI_REG_CONTROL8 0xc0
|
||||
#define SMI_REG_CONTROL9 0xc4
|
||||
|
||||
#define SMI_MODE_MASK 0x03
|
||||
|
||||
#endif /* AMD_TURIN_POC_SMI_H */
|
||||
23
src/soc/amd/turin_poc/include/soc/smu.h
Normal file
23
src/soc/amd/turin_poc/include/soc/smu.h
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef AMD_GENOA_POC_SMU_H
|
||||
#define AMD_GENOA_POC_SMU_H
|
||||
|
||||
/* SMU mailbox register offsets in SMN */
|
||||
#define SMN_SMU_MESG_ID 0x3b10530
|
||||
#define SMN_SMU_MESG_RESP 0x3b1057c
|
||||
#define SMN_SMU_MESG_ARGS_BASE 0x3b109c4
|
||||
|
||||
#define SMU_NUM_ARGS 6
|
||||
|
||||
enum smu_message_id {
|
||||
SMC_MSG_S3ENTRY = 0x0b,
|
||||
};
|
||||
|
||||
/*
|
||||
* Request the SMU put system into S3, S4, or S5. On entry, SlpTyp determines S-State and
|
||||
* SlpTypeEn gets set by the SMU. Function does not return if successful.
|
||||
*/
|
||||
void smu_sx_entry(void);
|
||||
|
||||
#endif /* AMD_GENOA_POC_SMU_H */
|
||||
8
src/soc/amd/turin_poc/include/soc/soc_chip.h
Normal file
8
src/soc/amd/turin_poc/include/soc/soc_chip.h
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _SOC_TURIN_POC_SOC_CHIP_H_
|
||||
#define _SOC_TURIN_POC_SOC_CHIP_H_
|
||||
|
||||
#include "../../chip.h"
|
||||
|
||||
#endif /* _SOC_TURIN_POC_SOC_CHIP_H_ */
|
||||
122
src/soc/amd/turin_poc/include/soc/southbridge.h
Normal file
122
src/soc/amd/turin_poc/include/soc/southbridge.h
Normal file
|
|
@ -0,0 +1,122 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef AMD_GENOA_POC_SOUTHBRIDGE_H
|
||||
#define AMD_GENOA_POC_SOUTHBRIDGE_H
|
||||
|
||||
#include <soc/iomap.h>
|
||||
|
||||
/* Power management registers: 0xfed80300 or index/data at IO 0xcd6/cd7 */
|
||||
#define PM_ISACONTROL 0x04
|
||||
#define ABCLKGATEEN BIT(16)
|
||||
#define PM_PCI_CTRL 0x08
|
||||
#define FORCE_SLPSTATE_RETRY BIT(25)
|
||||
#define PWR_RESET_CFG 0x10
|
||||
#define TOGGLE_ALL_PWR_GOOD (1 << 1)
|
||||
#define PM_SERIRQ_CONF 0x54
|
||||
#define PM_SERIRQ_NUM_BITS_17 0x0000
|
||||
#define PM_SERIRQ_NUM_BITS_18 0x0004
|
||||
#define PM_SERIRQ_NUM_BITS_19 0x0008
|
||||
#define PM_SERIRQ_NUM_BITS_20 0x000c
|
||||
#define PM_SERIRQ_NUM_BITS_21 0x0010
|
||||
#define PM_SERIRQ_NUM_BITS_22 0x0014
|
||||
#define PM_SERIRQ_NUM_BITS_23 0x0018
|
||||
#define PM_SERIRQ_NUM_BITS_24 0x001c
|
||||
#define PM_SERIRQ_MODE BIT(6)
|
||||
#define PM_SERIRQ_ENABLE BIT(7)
|
||||
#define PM_EVT_BLK 0x60
|
||||
#define WAK_STS BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */
|
||||
#define PCIEXPWAK_STS BIT(14)
|
||||
#define RTC_STS BIT(10)
|
||||
#define PWRBTN_STS BIT(8)
|
||||
#define GBL_STS BIT(5)
|
||||
#define BM_STS BIT(4)
|
||||
#define TIMER_STS BIT(0)
|
||||
#define PCIEXPWAK_DIS BIT(14) /*AcpiPmEvtBlkx02 Pm1Enable */
|
||||
#define RTC_EN BIT(10)
|
||||
#define PWRBTN_EN BIT(8)
|
||||
#define GBL_EN BIT(5)
|
||||
#define TIMER_STS BIT(0)
|
||||
#define PM1_CNT_BLK 0x62
|
||||
#define PM_TMR_BLK 0x64
|
||||
#define PM_GPE0_BLK 0x68
|
||||
#define PM_ACPI_SMI_CMD 0x6a
|
||||
#define PM_ACPI_CONF 0x74
|
||||
#define PM_ACPI_DECODE_STD BIT(0)
|
||||
#define PM_ACPI_GLOBAL_EN BIT(1)
|
||||
#define PM_ACPI_RTC_EN_EN BIT(2)
|
||||
#define PM_ACPI_SLPBTN_EN_EN BIT(3)
|
||||
#define PM_ACPI_TIMER_EN_EN BIT(4)
|
||||
#define PM_ACPI_MASK_ARB_DIS BIT(6)
|
||||
#define PM_ACPI_BIOS_RLS BIT(7)
|
||||
#define PM_ACPI_PWRBTNEN_EN BIT(8)
|
||||
#define PM_ACPI_REDUCED_HW_EN BIT(9)
|
||||
#define PM_ACPI_S5_LPC_PIN_MODE_SEL BIT(10)
|
||||
#define PM_ACPI_S5_LPC_PIN_MODE BIT(11)
|
||||
#define PM_ACPI_LPC_RST_DIS BIT(12)
|
||||
#define PM_ACPI_SEL_PWRGD_PAD BIT(13)
|
||||
#define PM_ACPI_SEL_SMU_THERMTRIP BIT(14)
|
||||
#define PM_ACPI_SW_S5PWRMUX_OVRD_N BIT(15)
|
||||
#define PM_ACPI_SW_S5PWRMUX BIT(16)
|
||||
#define PM_ACPI_EN_SHUTDOWN_MSG BIT(17)
|
||||
#define PM_ACPI_EN_SYNC_FLOOD BIT(18)
|
||||
#define PM_ACPI_FORCE_SPIUSEPIN_0 BIT(19)
|
||||
#define PM_ACPI_EN_DF_INTRWAKE BIT(20)
|
||||
#define PM_ACPI_MASK_USB_S5_RST BIT(21)
|
||||
#define PM_ACPI_USE_RSMU_RESET BIT(22)
|
||||
#define PM_ACPI_RST_USB_S5 BIT(23)
|
||||
#define PM_ACPI_BLOCK_PCIE_PME BIT(24)
|
||||
#define PM_ACPI_PCIE_WAK_MASK BIT(25)
|
||||
#define PM_ACPI_PCIE_WAK_INTR_DIS BIT(26)
|
||||
#define PM_ACPI_WAKE_AS_GEVENT BIT(27)
|
||||
#define PM_ACPI_NB_PME_GEVENT BIT(28)
|
||||
#define PM_ACPI_RTC_WAKE_EN BIT(29)
|
||||
#define PM_ACPI_USE_GATED_ALINK_CLK BIT(30)
|
||||
#define PM_ACPI_DELAY_GPP_OFF_TIME BIT(31)
|
||||
#define PM_SPI_PAD_PU_PD 0x90
|
||||
#define PM_ESPI_CS_USE_DATA2 BIT(16)
|
||||
#define PM_LPC_GATING 0xec
|
||||
#define PM_LPC_AB_NO_BYPASS_EN BIT(2)
|
||||
#define PM_LPC_A20_EN BIT(1)
|
||||
#define PM_LPC_ENABLE BIT(0)
|
||||
|
||||
#define PM1_LIMIT 16
|
||||
#define GPE0_LIMIT 32
|
||||
#define TOTAL_BITS(a) (8 * sizeof(a))
|
||||
|
||||
#define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */
|
||||
|
||||
/* FCH MISC Registers 0xfed80e00 */
|
||||
#define GPP_CLK_CNTRL 0x00
|
||||
#define GPP_CLK0_REQ_SHIFT 0
|
||||
#define GPP_CLK1_REQ_SHIFT 2
|
||||
#define GPP_CLK4_REQ_SHIFT 4
|
||||
#define GPP_CLK2_REQ_SHIFT 6
|
||||
#define GPP_CLK3_REQ_SHIFT 8
|
||||
#define GPP_CLK5_REQ_SHIFT 10
|
||||
#define GPP_CLK6_REQ_SHIFT 12
|
||||
#define GPP_CLK_OUTPUT_COUNT 7
|
||||
#define GPP_CLK_OUTPUT_AVAILABLE 4
|
||||
#define GPP_CLK_REQ_MASK(clk_shift) (0x3 << (clk_shift))
|
||||
#define GPP_CLK_REQ_ON(clk_shift) (0x3 << (clk_shift))
|
||||
#define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift))
|
||||
#define GPP_CLK_REQ_OFF(clk_shift) (0x0 << (clk_shift))
|
||||
|
||||
#define MISC_CLKGATEDCNTL 0x2c
|
||||
#define ALINKCLK_GATEOFFEN BIT(16)
|
||||
#define BLINKCLK_GATEOFFEN BIT(17)
|
||||
#define XTAL_PAD_S0I3_TURNOFF_EN BIT(19)
|
||||
#define XTAL_PAD_S3_TURNOFF_EN BIT(20)
|
||||
#define XTAL_PAD_S5_TURNOFF_EN BIT(21)
|
||||
#define MISC_CGPLL_CONFIGURATION0 0x30
|
||||
#define USB_PHY_CMCLK_S3_DIS BIT(8)
|
||||
#define USB_PHY_CMCLK_S0I3_DIS BIT(9)
|
||||
#define USB_PHY_CMCLK_S5_DIS BIT(10)
|
||||
#define MISC_CLK_CNTL0 0x40 /* named MISC_CLK_CNTL1 on Picasso */
|
||||
#define BP_X48M0_S0I3_DIS BIT(4)
|
||||
#define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */
|
||||
|
||||
void fch_pre_init(void);
|
||||
void fch_early_init(void);
|
||||
void fch_init(void *chip_info);
|
||||
|
||||
#endif /* AMD_GENOA_POC_SOUTHBRIDGE_H */
|
||||
10
src/soc/amd/turin_poc/include/soc/uart.h
Normal file
10
src/soc/amd/turin_poc/include/soc/uart.h
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef AMD_TURIN_POC_UART_H
|
||||
#define AMD_TURIN_POC_UART_H
|
||||
|
||||
#include <types.h>
|
||||
|
||||
void clear_uart_legacy_config(void); /* disable legacy I/O decode for FCH UART */
|
||||
|
||||
#endif /* AMD_TURIN_POC_UART_H */
|
||||
59
src/soc/amd/turin_poc/mca.c
Normal file
59
src/soc/amd/turin_poc/mca.c
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <amdblocks/mca.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <types.h>
|
||||
|
||||
/* TODO: Check if non-core MCA banks are same for all cores */
|
||||
static const char *const mca_bank_name[] = {
|
||||
[0] = "Load-store unit",
|
||||
[1] = "Instruction fetch unit",
|
||||
[2] = "L2 cache unit",
|
||||
[3] = "Decode unit",
|
||||
[4] = "",
|
||||
[5] = "Execution unit",
|
||||
[6] = "Floating point unit",
|
||||
[7] = "L3 cache unit",
|
||||
[8] = "L3 cache unit",
|
||||
[9] = "L3 cache unit",
|
||||
[10] = "L3 cache unit",
|
||||
[11] = "L3 cache unit",
|
||||
[12] = "L3 cache unit",
|
||||
[13] = "L3 cache unit",
|
||||
[14] = "L3 cache unit",
|
||||
[15] = "Microprocessor5 Management Controller",
|
||||
[16] = "Parameter Block",
|
||||
[17] = "GMI Controller",
|
||||
[18] = "GMI Controller",
|
||||
[19] = "High Speed Interface Unit (GMI)",
|
||||
[20] = "High Speed Interface Unit (GMI)",
|
||||
[21] = "Unified Memory Controller",
|
||||
[22] = "Unified Memory Controller",
|
||||
[23] = "Coherent Station",
|
||||
[24] = "Coherent Station",
|
||||
[25] = "Northbridge IO Unit",
|
||||
[26] = "PCIe Root Port",
|
||||
[27] = "PCIe Root Port",
|
||||
[28] = "Power Management, Interrupts, Etc.",
|
||||
[29] = "SMU",
|
||||
[30] = "XGMI Controller",
|
||||
[31] = "High Speed Interface Unit (XGMI)",
|
||||
};
|
||||
|
||||
bool mca_has_expected_bank_count(void)
|
||||
{
|
||||
return ARRAY_SIZE(mca_bank_name) == mca_get_bank_count();
|
||||
}
|
||||
|
||||
bool mca_is_valid_bank(unsigned int bank)
|
||||
{
|
||||
return (bank < ARRAY_SIZE(mca_bank_name) && mca_bank_name[bank] != NULL);
|
||||
}
|
||||
|
||||
const char *mca_get_bank_name(unsigned int bank)
|
||||
{
|
||||
if (mca_is_valid_bank(bank))
|
||||
return mca_bank_name[bank];
|
||||
else
|
||||
return "";
|
||||
}
|
||||
27
src/soc/amd/turin_poc/reset.c
Normal file
27
src/soc/amd/turin_poc/reset.c
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <cf9_reset.h>
|
||||
#include <reset.h>
|
||||
#include <soc/southbridge.h>
|
||||
#include <amdblocks/acpimmio.h>
|
||||
#include <amdblocks/reset.h>
|
||||
|
||||
void do_cold_reset(void)
|
||||
{
|
||||
/* De-assert and then assert all PwrGood signals on CF9 reset. */
|
||||
pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) |
|
||||
TOGGLE_ALL_PWR_GOOD);
|
||||
outb(RST_CPU | SYS_RST, RST_CNT);
|
||||
}
|
||||
|
||||
void do_warm_reset(void)
|
||||
{
|
||||
/* Warm resets are not supported and must be executed as cold */
|
||||
do_cold_reset();
|
||||
}
|
||||
|
||||
void do_board_reset(void)
|
||||
{
|
||||
do_cold_reset();
|
||||
}
|
||||
51
src/soc/amd/turin_poc/root_complex.c
Normal file
51
src/soc/amd/turin_poc/root_complex.c
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <amdblocks/ioapic.h>
|
||||
#include <amdblocks/root_complex.h>
|
||||
#include <types.h>
|
||||
|
||||
static const struct domain_iohc_info iohc_info[] = {
|
||||
[0] = {
|
||||
.fabric_id = 0x22,
|
||||
.misc_smn_base = SMN_IOHC_MISC_BASE_13C1,
|
||||
},
|
||||
[1] = {
|
||||
.fabric_id = 0x23,
|
||||
.misc_smn_base = SMN_IOHC_MISC_BASE_13B1,
|
||||
},
|
||||
[2] = {
|
||||
.fabric_id = 0x21,
|
||||
.misc_smn_base = SMN_IOHC_MISC_BASE_13E1,
|
||||
},
|
||||
[3] = {
|
||||
.fabric_id = 0x20,
|
||||
.misc_smn_base = SMN_IOHC_MISC_BASE_13D1,
|
||||
},
|
||||
};
|
||||
|
||||
const struct domain_iohc_info *get_iohc_info(size_t *count)
|
||||
{
|
||||
*count = ARRAY_SIZE(iohc_info);
|
||||
return iohc_info;
|
||||
}
|
||||
|
||||
static const struct non_pci_mmio_reg non_pci_mmio[] = {
|
||||
{ 0x2d8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO },
|
||||
{ 0x2e0, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO },
|
||||
{ 0x2e8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO },
|
||||
/* The hardware has a 256 byte alignment requirement for the IOAPIC MMIO base, but we
|
||||
tell the FSP to configure a 4k-aligned base address and this is reported as 4 KiB
|
||||
resource. */
|
||||
{ 0x2f0, 0xffffffffff00ull, 4 * KiB, IOMMU_IOAPIC_IDX },
|
||||
{ 0x2f8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO },
|
||||
{ 0x300, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO },
|
||||
{ 0x308, 0xfffffffff000ull, 4 * KiB, NON_PCI_RES_IDX_AUTO },
|
||||
{ 0x310, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO },
|
||||
{ 0x318, 0xfffffff80000ull, 512 * KiB, NON_PCI_RES_IDX_AUTO },
|
||||
};
|
||||
|
||||
const struct non_pci_mmio_reg *get_iohc_non_pci_mmio_regs(size_t *count)
|
||||
{
|
||||
*count = ARRAY_SIZE(non_pci_mmio);
|
||||
return non_pci_mmio;
|
||||
}
|
||||
96
src/soc/amd/turin_poc/smihandler.c
Normal file
96
src/soc/amd/turin_poc/smihandler.c
Normal file
|
|
@ -0,0 +1,96 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <acpi/acpi.h>
|
||||
#include <amdblocks/acpi.h>
|
||||
#include <amdblocks/acpimmio.h>
|
||||
#include <amdblocks/psp.h>
|
||||
#include <amdblocks/smi.h>
|
||||
#include <amdblocks/smm.h>
|
||||
#include <arch/hlt.h>
|
||||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <soc/smi.h>
|
||||
#include <soc/smu.h>
|
||||
#include <soc/southbridge.h>
|
||||
#include <types.h>
|
||||
|
||||
/*
|
||||
* Both the psp_notify_sx_info and the smu_sx_entry call will clobber the SMN index register
|
||||
* during the SMN accesses. Since the SMI handler is the last thing that gets called before
|
||||
* entering S3, this won't interfere with any indirect SMN accesses via the same register pair.
|
||||
*/
|
||||
static void fch_slp_typ_handler(void)
|
||||
{
|
||||
uint32_t pci_ctrl;
|
||||
uint16_t pm1cnt;
|
||||
uint8_t slp_typ, rst_ctrl;
|
||||
|
||||
/* Figure out SLP_TYP */
|
||||
pm1cnt = acpi_read16(MMIO_ACPI_PM1_CNT_BLK);
|
||||
printk(BIOS_SPEW, "SMI#: SLP = 0x%04x\n", pm1cnt);
|
||||
slp_typ = acpi_sleep_from_pm1(pm1cnt);
|
||||
|
||||
/* Do any mainboard sleep handling */
|
||||
mainboard_smi_sleep(slp_typ);
|
||||
|
||||
switch (slp_typ) {
|
||||
case ACPI_S0:
|
||||
printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n");
|
||||
break;
|
||||
case ACPI_S3:
|
||||
printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
|
||||
break;
|
||||
case ACPI_S4:
|
||||
printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n");
|
||||
break;
|
||||
case ACPI_S5:
|
||||
printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n");
|
||||
break;
|
||||
}
|
||||
|
||||
if (slp_typ >= ACPI_S3) {
|
||||
wbinvd();
|
||||
|
||||
clear_all_smi_status();
|
||||
|
||||
/* Do not send SMI before AcpiPm1CntBlkx00[SlpTyp] */
|
||||
pci_ctrl = pm_read32(PM_PCI_CTRL);
|
||||
pci_ctrl &= ~FORCE_SLPSTATE_RETRY;
|
||||
pm_write32(PM_PCI_CTRL, pci_ctrl);
|
||||
|
||||
/* Enable SlpTyp */
|
||||
rst_ctrl = pm_read8(PM_RST_CTRL1);
|
||||
rst_ctrl |= SLPTYPE_CONTROL_EN;
|
||||
pm_write8(PM_RST_CTRL1, rst_ctrl);
|
||||
|
||||
smu_sx_entry(); /* Leave SlpTypeEn clear, SMU will set */
|
||||
printk(BIOS_ERR, "System did not go to sleep\n");
|
||||
hlt();
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Table of functions supported in the SMI handler. Note that SMI source setup
|
||||
* in fch.c is unrelated to this list.
|
||||
*/
|
||||
static const struct smi_sources_t smi_sources[] = {
|
||||
{ .type = SMITYPE_SMI_CMD_PORT, .handler = fch_apmc_smi_handler },
|
||||
{ .type = SMITYPE_SLP_TYP, .handler = fch_slp_typ_handler},
|
||||
{ .type = SMITYPE_PSP, .handler = psp_smi_handler },
|
||||
};
|
||||
|
||||
void *get_smi_source_handler(int source)
|
||||
{
|
||||
size_t i;
|
||||
|
||||
for (i = 0 ; i < ARRAY_SIZE(smi_sources) ; i++)
|
||||
if (smi_sources[i].type == source)
|
||||
return smi_sources[i].handler;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
38
src/soc/amd/turin_poc/uart.c
Normal file
38
src/soc/amd/turin_poc/uart.c
Normal file
|
|
@ -0,0 +1,38 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/mmio.h>
|
||||
#include <amdblocks/gpio.h>
|
||||
#include <amdblocks/uart.h>
|
||||
#include <commonlib/helpers.h>
|
||||
#include <soc/aoac_defs.h>
|
||||
#include <gpio.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <soc/southbridge.h>
|
||||
#include <soc/uart.h>
|
||||
#include <types.h>
|
||||
|
||||
static const struct soc_uart_ctrlr_info uart_info[] = {
|
||||
[0] = { APU_UART0_BASE, FCH_AOAC_DEV_UART0, "FUR0", {
|
||||
PAD_NF(GPIO_136, UART0_RXD, PULL_NONE),
|
||||
PAD_NF(GPIO_138, UART0_TXD, PULL_NONE),
|
||||
} },
|
||||
[1] = { APU_UART1_BASE, FCH_AOAC_DEV_UART1, "FUR1", {
|
||||
PAD_NF(GPIO_141, UART1_RXD, PULL_NONE),
|
||||
PAD_NF(GPIO_142, UART1_TXD, PULL_NONE),
|
||||
} },
|
||||
[2] = { APU_UART2_BASE, FCH_AOAC_DEV_UART2, "FUR2", {
|
||||
PAD_NF(GPIO_137, UART2_RXD, PULL_NONE),
|
||||
PAD_NF(GPIO_135, UART2_TXD, PULL_NONE),
|
||||
} },
|
||||
};
|
||||
|
||||
const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs)
|
||||
{
|
||||
*num_ctrlrs = ARRAY_SIZE(uart_info);
|
||||
return uart_info;
|
||||
}
|
||||
|
||||
void clear_uart_legacy_config(void)
|
||||
{
|
||||
write16((void *)FCH_LEGACY_UART_DECODE, 0);
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue