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soc/qualcomm/x1p42100: Add NVMe Power Loss Notification GPIO configuration

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Add support for configuring the NVMe Power Loss Notification (PLN)
GPIO before powering on the NVMe device.

The Hamoa target has the PLN signal wired to SoC GPIO 157. The voltage
level conversion circuitry between the SoC (1.2V) and NVMe (3.3V) causes
the PLN signal voltage level to vary depending on the NVMe part used.

This change configures GPIO 157 as an input with no pull resistors and
2mA drive strength to ensure proper PLN signal handling and allow the
GPIO to be used for other hardware configurations.

Changes:
- Add NVME_PLN_GPIO definition for GPIO(157)
- Add nvme_core_pln_gpio() function to configure PLN GPIO
- Update gcom_pcie_power_on_ep() to call nvme_core_pln_gpio() before
  enabling NVMe power regulator

TEST=Boot the Google/Bluey board and verify NVMe device is detected
and functional

Debug logs:

Initializing NVMe controller 1e0f:000c
nvme_ctrlr_init: PCI Command register = 0x2
nvme_ctrlr_init: PCI Status register = 0x10
nvme_ctrlr_init: PCI Command after bus master enable = 0x6
iosq_sz = 11, iocq_sz = 11
nvme_wait_status: Waiting for CSTS & 0x1 == 0x0, timeout=30000 ms
nvme_ctrlr_init: Waited 100ms after controller disable
nvme_enable_controller: CSTS before enable = 0x0
nvme_enable_controller: CAP register = 0x303c03ffff
nvme_enable_controller: CAP.TO timeout = 30000 ms
nvme_enable_controller: Writing CC register = 0x460001
nvme_enable_controller: CC register readback = 0x460001
nvme_wait_status: Waiting for CSTS & 0x1 == 0x1, timeout=30000 ms
nvme_enable_controller: CSTS after enable = 0x1 (status=0)
Identified NVMe model KBG50ZNS256G KIOXIA
Added NVMe drive "NVMe Namespace 1" lbasize:512, count:0x1dcf32b0

Change-Id: Icc22cfd397a0adbc051b2b1a2178aeedb7389ac0
Signed-off-by: Hari L <haril@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90037
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Hari L 2025-11-14 14:31:16 +05:30 • committed by Matt DeVillier
commit 62fc93de90
1 changed files with 23 additions and 0 deletions
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23
src/soc/qualcomm/x1p42100/pcie.c
View file

@ -11,6 +11,7 @@
#include <soc/pcie.h>
#define NVME_REG_EN GPIO(18)
#define NVME_PLN_GPIO GPIO(157) /* Power Loss Notification */
static const struct qcom_qmp_phy_init_tbl x1p42100_qmp_pcie_serdes_pll_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_PLL_SSC_STEP_SIZE1_MODE1, 0x26),
@ -301,9 +302,31 @@ int32_t qcom_dw_pcie_enable_clock(void)
return ret;
}
/*
* Configure NVMe Power Loss Notification GPIO
*
* Hamoa target wired the PLN signal to a SoC GPIO. The circuitry
* for connecting the PLN from the SoC (1.2volts) to the NVMe (3.3volts)
* caused the voltage level on the PLN signal on the NVMe side to be
* different depending on the NVMe part. This function will Configure PLN
* GPIO in software to make sure the PLN is high and this GPIO can be used
* for other HW configurations.
*/
static void nvme_core_pln_gpio(void)
{
gpio_configure(NVME_PLN_GPIO, /* GPIO 157 */
GPIO_FUNC_GPIO, /* Function, 0 for generic */
GPIO_NO_PULL, /* Pull */
GPIO_2MA, /* Drive strength */
GPIO_INPUT); /* Direction */
}
/* Turn on NVMe */
void gcom_pcie_power_on_ep(void)
{
/* Configure Power Loss Notification GPIO before powering on */
nvme_core_pln_gpio();
gpio_output(NVME_REG_EN, 1);
}