Subrata Banik d277b35307 soc/qualcomm/x1p42100: Relocate ddr_information and watchdog tombstone ... This commit relocates the following two regions: 1. `ddr_information` 2. `WATCHDOG_TOMBSTONE` Previously, these regions were allocated in a higher address range (starting near 0x14800000). The regions are now defined within SSRAM`: - `ddr_information` is moved from `0x14860000` to `0x146ABFE8`. - `WATCHDOG_TOMBSTONE` is moved from `0x14818FFC` to `0x146ABFFC`. This memory map change updates the linker script's visual diagram and section definitions to reflect the new memory layout. BUG=b:456953373 TEST=Able to build google/quenbi. Change-Id: I4545722a836ec472e8086d1a941515cb3956c763 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90052 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2025-11-22 17:24:13 +00:00
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amd	soc/amd/cezanne: Add SOC_AMD_RENOIR as a Cezanne variant	2025-11-20 17:39:08 +00:00
cavium
example/min86
ibm/power9	soc/power9/rom_media.c: find CBFS in PNOR	2025-08-28 20:14:01 +00:00
intel	soc/intel/pantherlake/romstage: Configure VGA mode 12 monochrome buffer	2025-11-19 13:56:41 +00:00
mediatek	soc/mediatek/mt8196: Add dual display pipe path	2025-11-18 07:37:31 +00:00
nvidia
qualcomm	soc/qualcomm/x1p42100: Relocate ddr_information and watchdog tombstone	2025-11-22 17:24:13 +00:00
rockchip
samsung	samsung/exynos5250: Replace 'unsigned long int' by 'unsigned long'	2025-01-15 08:32:16 +00:00
sifive
ti
ucb/riscv	soc/riscv/ucb: Switch to FDT parsing to get memory size	2025-02-26 17:11:09 +00:00
xilinx	soc/xilinx/zynq7000: Initial Xilinx Zynq 7000 SoC bringup	2025-01-23 00:41:01 +00:00