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soc/amd/cezanne: Add SOC_AMD_RENOIR as a Cezanne variant

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AMD Renoir soc is very similar to Cezanne and has been used without
differentiation until now. Create the separation between SOCs using
Kconfig option to facilitate the customization of different features.
Also update SOC_AMD_RENOIR use on the crater mainboard.

Change-Id: I4783c4e3b17032b6d26ef67ddf954df3ce68fdf0
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87215
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Ana Carolina Cabral 2025-03-28 09:48:04 -03:00 • committed by Matt DeVillier
commit a48fd9ed7f
5 changed files with 73 additions and 6 deletions
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2
src/mainboard/amd/crater/Kconfig
View file

@ -22,7 +22,7 @@ config BOARD_AMD_CRATER_COMMON
config BOARD_AMD_CRATER_RENOIR
select BOARD_AMD_CRATER_COMMON
select SOC_AMD_CEZANNE
select SOC_AMD_RENOIR
if BOARD_AMD_CRATER_RENOIR

25
src/soc/amd/cezanne/Kconfig
View file

@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
config SOC_AMD_CEZANNE
config SOC_AMD_CEZANNE_BASE
bool
select ACPI_SOC_NVS
select ADD_FSP_BINARIES if USE_AMD_BLOBS
@ -91,7 +91,19 @@ config SOC_AMD_CEZANNE
help
AMD Cezanne support
if SOC_AMD_CEZANNE
config SOC_AMD_CEZANNE
bool
select SOC_AMD_CEZANNE_BASE
help
AMD Cezanne support
config SOC_AMD_RENOIR
bool
select SOC_AMD_CEZANNE_BASE
help
AMD Renoir support
if SOC_AMD_CEZANNE_BASE
config KEEP_ACP_RUNNING_IN_S3
bool
@ -107,6 +119,7 @@ config CHIPSET_DEVICETREE
config FSP_M_FILE
string "FSP-M (memory init) binary path and filename"
depends on ADD_FSP_BINARIES
#default "3rdparty/amd_blobs/renoir/RENOIR_M.fd" if SOC_AMD_RENOIR
default "3rdparty/amd_blobs/cezanne/CEZANNE_M.fd"
help
The path and filename of the FSP-M binary for this platform.
@ -114,6 +127,7 @@ config FSP_M_FILE
config FSP_S_FILE
string "FSP-S (silicon init) binary path and filename"
depends on ADD_FSP_BINARIES
#default "3rdparty/amd_blobs/renoir/RENOIR_S.fd" if SOC_AMD_RENOIR
default "3rdparty/amd_blobs/cezanne/CEZANNE_S.fd"
help
The path and filename of the FSP-S binary for this platform.
@ -256,6 +270,7 @@ config RO_REGION_ONLY
default "apu/amdfw"
config ECAM_MMCONF_BASE_ADDRESS
default 0xE0000000 if SOC_AMD_RENOIR
default 0xF8000000
config ECAM_MMCONF_BUS_NUMBER
@ -269,6 +284,7 @@ config MAX_CPUS
config VGA_BIOS_ID
string
default "1002,1636" if SOC_AMD_RENOIR
default "1002,1638"
help
The default VGA BIOS PCI vendor/device ID should be set to the
@ -276,6 +292,7 @@ config VGA_BIOS_ID
config VGA_BIOS_FILE
string
#default "3rdparty/amd_blobs/renoir/RenoirGenericVbios.bin" if SOC_AMD_RENOIR
default "3rdparty/amd_blobs/cezanne/CezanneGenericVbios.bin"
config CONSOLE_UART_BASE_ADDRESS
@ -337,6 +354,7 @@ menu "PSP Configuration Options"
config AMDFW_CONFIG_FILE
string
#default "src/soc/amd/cezanne/fw_renoir.cfg" if SOC_AMD_RENOIR
default "src/soc/amd/cezanne/fw.cfg"
config PSP_DISABLE_POSTCODES
@ -385,6 +403,7 @@ config HAVE_PSP_WHITELIST_FILE
config PSP_WHITELIST_FILE
string "Debug whitelist file path"
depends on HAVE_PSP_WHITELIST_FILE
#default "3rdparty/amd_blobs/renoir/PSP/wtl-rn.sbin" if SOC_AMD_RENOIR
default "3rdparty/amd_blobs/cezanne/PSP/wtl-czn.sbin"
config PSP_SOFTFUSE_BITS
@ -492,4 +511,4 @@ config SERIRQ_CONTINUOUS_MODE
Set this option to y for serial IRQ in continuous mode.
Otherwise it is in quiet mode.
endif # SOC_AMD_CEZANNE
endif # SOC_AMD_CEZANNE_BASE

4
src/soc/amd/cezanne/Makefile.mk
View file

@ -1,6 +1,6 @@
# SPDX-License-Identifier: BSD-3-Clause
ifeq ($(CONFIG_SOC_AMD_CEZANNE),y)
ifeq ($(CONFIG_SOC_AMD_CEZANNE_BASE),y)
subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage
@ -285,4 +285,4 @@ apu/amdfw_b-position := $(AMD_FW_AB_POSITION)
apu/amdfw_b-type := raw
endif
endif # ($(CONFIG_SOC_AMD_CEZANNE),y)
endif # ($(CONFIG_SOC_AMD_CEZANNE_BASE),y)

4
src/soc/amd/cezanne/chip.c
View file

@ -53,7 +53,11 @@ static void soc_final(void *chip_info)
}
struct chip_operations soc_amd_cezanne_ops = {
#if CONFIG(SOC_AMD_CEZANNE)
.name = "AMD Cezanne SoC",
#elif CONFIG(SOC_AMD_RENOIR)
.name = "AMD Renoir SoC",
#endif
.init = soc_init,
.final = soc_final
};

44
src/soc/amd/cezanne/fw_renoir.cfg Normal file
View file

@ -0,0 +1,44 @@
#TODO update for renoir
# PSP fw config file
FIRMWARE_LOCATION 3rdparty/amd_blobs/cezanne/PSP
SOC_NAME Renoir
# type file
# PSP
AMD_PUBKEY_FILE TypeId0x00_CezannePublicKey.tkn Lxb
PSPBTLDR_FILE TypeId0x01_PspBootLoader_CZN.sbin
PSPBTLDR_AB_STAGE1_FILE TypeId0x01_PspBootLoader_AB_Stage1_CZN.sbin Lx1
PSPBTLDR_WL_FILE TypeId0x01_PspBootLoader_WL_CZN.sbin
PSPSECUREOS_FILE TypeId0x02_PspOS_CZN.sbin
PSPRCVR_FILE TypeId0x03_PspRecoveryBootLoader_CZN.sbin
PSP_SMUFW1_SUB0_FILE TypeId0x08_SmuFirmware_CZN.csbin
PSPSECUREDEBUG_FILE TypeId0x09_SecureDebugUnlockKey_CZN.stkn
PSPTRUSTLETS_FILE TypeId0x0C_FtpmDrv_CZN.csbin
PSP_SMUFW2_SUB0_FILE TypeId0x12_SmuFirmware2_CZN.csbin
PSP_SEC_DEBUG_FILE TypeId0x13_PspEarlyUnlock_CZN.sbin
PSP_HW_IPCFG_FILE_SUB0 TypeId0x20_HwIpCfg_CZN_A0.sbin
PSP_IKEK_FILE TypeId0x21_PspIkek_CZN.bin Lxb
PSP_SECG0_FILE TypeId0x24_SecurePolicyL0_CZN.sbin
PSP_MP2FW0_FILE TypeId0x25_Mp2Fw_CZN.sbin
AMD_DRIVER_ENTRIES TypeId0x28_PspSystemDriver_CZN.sbin
PSP_KVM_ENGINE_DUMMY_FILE TypeId0x29_KvmEngineDummy.csbin
PSP_S0I3_FILE TypeId0x2D_AgesaRunTimeDrv_CZN.sbin
PSP_ABL0_FILE TypeId0x30_AgesaBootloaderU_CZN_LPDDR4.csbin
VBIOS_BTLOADER_FILE TypeId0x3C_VbiosBootLoader_CZN.sbin
SECURE_POLICY_L1_FILE TypeId0x45_SecurePolicyL1_CZN.sbin
UNIFIEDUSB_FILE TypeId0x44_UnifiedUsb_CZN.sbin
DRTMTA_FILE TypeId0x47_DrtmTA_CZN.sbin
KEYDBBL_FILE TypeId0x50_KeyDbBl_CZN.sbin
KEYDB_TOS_FILE TypeId0x51_KeyDbTos_CZN.sbin
SPL_TABLE_FILE TypeId0x55_SplTableBl_CZN.sbin
DMCUERAMDCN21_FILE TypeId0x58_DmcuEramDcn21.sbin
DMCUINTVECTORSDCN21_FILE TypeId0x59_DmcuIntvectorsDcn21.sbin
PSPBTLDR_AB_FILE TypeId0x73_PspBootLoader_AB_CZN.sbin
# BDT
PSP_PMUI_FILE_SUB0_INS1 TypeId0x64_Appb_CZN_1D_Lpddr4_Imem.csbin
PSP_PMUD_FILE_SUB0_INS1 TypeId0x65_Appb_CZN_1D_Lpddr4_Dmem.csbin
PSP_PMUI_FILE_SUB0_INS4 TypeId0x64_Appb_CZN_2D_Lpddr4_Imem.csbin
PSP_PMUD_FILE_SUB0_INS4 TypeId0x65_Appb_CZN_2D_Lpddr4_Dmem.csbin
PSP_MP2CFG_FILE MP2FWConfig.sbin