soc/mediatek/common: Add C-PHY support for MIPI DSI
Introduce C-PHY support by adding PANEL_FLAG_CPHY flag, updating data rate calculations, timing configurations, and register settings for C-PHY operation. To improve code reusability, the D-PHY and C-PHY specific implementations are moved to `mtk_mipi_dphy.c` and `mtk_mipi_cphy.c`, respectively. BUG=b:433422905,b:428854543 BRANCH=skywalker TEST=check log on padme mtk_display_init: 'TM TL121BVMS07' 1600x2560@60Hz Change-Id: I9e81551484e605e1d74b9983fe00b5d0eba69358 Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com> Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com> (cherry picked from commit 22a499836eeb6904e114023da6222b29da10f62f) Reviewed-on: https://review.coreboot.org/c/coreboot/+/89567 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Vince Liu
Yu-Ping Wu
parent
c63e901b99
commit
44635f328c
9 changed files with 309 additions and 113 deletions
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@ -54,6 +54,12 @@ config MEDIATEK_DRAM_SCRAMBLE
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This option enables DRAM data scramble, which can prevent DRAM data from
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being hacked.
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config MEDIATEK_DSI_CPHY
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bool
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default n
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help
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The configuration to support DSI C-PHY.
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config MEMORY_TEST
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bool
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default y
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@ -103,6 +103,7 @@ int mtk_display_init(void)
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const char *name;
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struct panel_description *panel = get_active_panel();
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uintptr_t fb_addr;
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u32 lanes;
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if (!panel || panel->disp_path == DISP_PATH_NONE) {
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printk(BIOS_ERR, "%s: Failed to get the active panel\n", __func__);
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@ -146,7 +147,14 @@ int mtk_display_init(void)
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MIPI_DSI_MODE_LPM |
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MIPI_DSI_MODE_EOT_PACKET);
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if (mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, &edid,
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if (mipi_data->flags & PANEL_FLAG_CPHY) {
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mipi_dsi_flags |= MIPI_DSI_MODE_CPHY;
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lanes = 3;
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} else {
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lanes = 4;
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}
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if (mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, lanes, &edid,
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mipi_data ? mipi_data->init : NULL) < 0) {
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printk(BIOS_ERR, "%s: Failed in DSI init\n", __func__);
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return -1;
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@ -12,6 +12,9 @@
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#define MIN_HFP_BYTE 2
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#define MIN_HBP_BYTE 2
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#define CPHY_SYMBOL_RATE 7
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#define CPHY_SYMBOL_RATE_DIVISOR 16
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static unsigned int mtk_dsi_get_bits_per_pixel(u32 format)
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{
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switch (format) {
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@ -29,7 +32,7 @@ static unsigned int mtk_dsi_get_bits_per_pixel(u32 format)
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}
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static u32 mtk_dsi_get_data_rate(u32 bits_per_pixel, u32 lanes,
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const struct edid *edid)
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const struct edid *edid, bool is_cphy)
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{
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/* data_rate = pixel_clock * bits_per_pixel * mipi_ratio / lanes
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* Note pixel_clock comes in kHz and returned data_rate is in bps.
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@ -37,11 +40,16 @@ static u32 mtk_dsi_get_data_rate(u32 bits_per_pixel, u32 lanes,
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* for older platforms which do not have complete implementation in HFP.
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* Newer platforms should just set that to 1.0 (100 / 100).
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*/
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u32 data_rate = DIV_ROUND_UP((u64)edid->mode.pixel_clock *
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bits_per_pixel * 1000 *
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MTK_DSI_MIPI_RATIO_NUMERATOR,
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(u64)lanes *
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MTK_DSI_MIPI_RATIO_DENOMINATOR);
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u32 data_rate;
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u64 dividend = (u64)edid->mode.pixel_clock * bits_per_pixel * 1000 *
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MTK_DSI_MIPI_RATIO_NUMERATOR;
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u64 divisor = (u64)lanes * MTK_DSI_MIPI_RATIO_DENOMINATOR;
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if (is_cphy) {
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dividend *= CPHY_SYMBOL_RATE;
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divisor *= CPHY_SYMBOL_RATE_DIVISOR;
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}
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data_rate = DIV_ROUND_UP(dividend, divisor);
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printk(BIOS_INFO, "DSI data_rate: %u bps\n", data_rate);
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if (data_rate < MTK_DSI_DATA_RATE_MIN_MHZ * MHz) {
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@ -63,13 +71,11 @@ __weak void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing)
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/* Do nothing. */
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}
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static void mtk_dsi_phy_timing(u32 data_rate, struct mtk_phy_timing *timing)
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static void mtk_dsi_dphy_timing(u32 data_rate, struct mtk_phy_timing *timing)
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{
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u32 timcon0, timcon1, timcon2, timcon3;
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u32 data_rate_mhz = DIV_ROUND_UP(data_rate, MHz);
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memset(timing, 0, sizeof(*timing));
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timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1;
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timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
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timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -
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@ -163,46 +169,19 @@ static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes)
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write32(&dsi0->dsi_txrx_ctrl, tmp_reg);
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}
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static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes,
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const struct edid *edid,
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const struct mtk_phy_timing *phy_timing)
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static void mtk_dsi_dphy_vdo_timing(const u32 mode_flags,
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const u32 lanes,
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const struct edid *edid,
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const struct mtk_phy_timing *phy_timing,
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const u32 bytes_per_pixel,
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const u32 hbp,
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const u32 hfp,
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s32 *hbp_byte,
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s32 *hfp_byte,
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u32 *hsync_active_byte)
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{
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u32 hsync_active_byte;
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u32 hbp;
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u32 hfp;
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s32 hbp_byte;
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s32 hfp_byte;
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u32 vbp_byte;
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u32 vfp_byte;
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u32 bytes_per_pixel;
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u32 packet_fmt;
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u32 hactive;
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u32 data_phy_cycles;
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bytes_per_pixel = DIV_ROUND_UP(mtk_dsi_get_bits_per_pixel(format), 8);
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vbp_byte = edid->mode.vbl - edid->mode.vso - edid->mode.vspw -
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edid->mode.vborder;
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vfp_byte = edid->mode.vso - edid->mode.vborder;
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write32(&dsi0->dsi_vsa_nl, edid->mode.vspw);
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write32(&dsi0->dsi_vbp_nl, vbp_byte);
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write32(&dsi0->dsi_vfp_nl, vfp_byte);
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write32(&dsi0->dsi_vact_nl, edid->mode.va);
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hsync_active_byte = edid->mode.hspw * bytes_per_pixel - 10;
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hbp = edid->mode.hbl - edid->mode.hso - edid->mode.hspw -
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edid->mode.hborder;
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hfp = edid->mode.hso - edid->mode.hborder;
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if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
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hbp_byte = hbp * bytes_per_pixel - 10;
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else
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hbp_byte = (hbp + edid->mode.hspw) * bytes_per_pixel - 10;
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hfp_byte = hfp * bytes_per_pixel;
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data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare +
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phy_timing->da_hs_zero + phy_timing->da_hs_exit + 3;
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u32 data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare +
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phy_timing->da_hs_zero + phy_timing->da_hs_exit + 3;
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u32 delta = 10;
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@ -217,20 +196,65 @@ static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes,
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d_phy = data_phy_cycles * lanes + delta;
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if ((hfp + hbp) * bytes_per_pixel > d_phy) {
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hfp_byte -= d_phy * hfp / (hfp + hbp);
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hbp_byte -= d_phy * hbp / (hfp + hbp);
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*hfp_byte -= d_phy * hfp / (hfp + hbp);
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*hbp_byte -= d_phy * hbp / (hfp + hbp);
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} else {
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printk(BIOS_ERR, "HFP %u plus HBP %u is not greater than d_phy %u, "
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"the panel may not work properly.\n", hfp * bytes_per_pixel,
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hbp * bytes_per_pixel, d_phy);
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"the panel may not work properly.\n", hfp * bytes_per_pixel,
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hbp * bytes_per_pixel, d_phy);
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}
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*hsync_active_byte = edid->mode.hspw * bytes_per_pixel - 10;
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if (mode_flags & MIPI_DSI_MODE_LINE_END) {
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hsync_active_byte = DIV_ROUND_UP(hsync_active_byte, lanes) * lanes - 2;
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hbp_byte = DIV_ROUND_UP(hbp_byte, lanes) * lanes - 2;
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hfp_byte = DIV_ROUND_UP(hfp_byte, lanes) * lanes - 2;
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hbp_byte -= (edid->mode.ha * bytes_per_pixel + 2) % lanes;
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*hsync_active_byte = DIV_ROUND_UP(*hsync_active_byte, lanes) * lanes - 2;
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*hbp_byte = DIV_ROUND_UP(*hbp_byte, lanes) * lanes - 2;
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*hfp_byte = DIV_ROUND_UP(*hfp_byte, lanes) * lanes - 2;
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*hbp_byte -= (edid->mode.ha * bytes_per_pixel + 2) % lanes;
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}
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}
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static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes,
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const struct edid *edid,
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const struct mtk_phy_timing *phy_timing)
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{
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u32 hsync_active_byte;
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u32 hbp;
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u32 hfp;
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s32 hbp_byte;
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s32 hfp_byte;
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u32 vbp_byte;
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u32 vfp_byte;
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u32 bytes_per_pixel;
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u32 packet_fmt;
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u32 hactive;
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bool is_cphy = !!(mode_flags & MIPI_DSI_MODE_CPHY);
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bytes_per_pixel = DIV_ROUND_UP(mtk_dsi_get_bits_per_pixel(format), 8);
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vbp_byte = edid->mode.vbl - edid->mode.vso - edid->mode.vspw -
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edid->mode.vborder;
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vfp_byte = edid->mode.vso - edid->mode.vborder;
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write32(&dsi0->dsi_vsa_nl, edid->mode.vspw);
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write32(&dsi0->dsi_vbp_nl, vbp_byte);
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write32(&dsi0->dsi_vfp_nl, vfp_byte);
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write32(&dsi0->dsi_vact_nl, edid->mode.va);
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hbp = edid->mode.hbl - edid->mode.hso - edid->mode.hspw -
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edid->mode.hborder;
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hfp = edid->mode.hso - edid->mode.hborder;
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if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
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hbp_byte = hbp * bytes_per_pixel - 10;
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else
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hbp_byte = (hbp + edid->mode.hspw) * bytes_per_pixel - 10;
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hfp_byte = hfp * bytes_per_pixel;
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if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
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mtk_dsi_cphy_vdo_timing(lanes, edid, phy_timing, bytes_per_pixel, hbp, hfp,
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&hbp_byte, &hfp_byte, &hsync_active_byte);
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else
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mtk_dsi_dphy_vdo_timing(mode_flags, lanes, edid, phy_timing, bytes_per_pixel,
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hbp, hfp, &hbp_byte, &hfp_byte, &hsync_active_byte);
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if (hfp_byte + hbp_byte < MIN_HFP_BYTE + MIN_HBP_BYTE) {
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printk(BIOS_ERR, "Calculated hfp_byte %d and hbp_byte %d are too small, "
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@ -281,6 +305,8 @@ static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, u32 lanes,
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write32(&dsi0->dsi_size_con,
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edid->mode.va << DSI_SIZE_CON_HEIGHT_SHIFT |
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hactive << DSI_SIZE_CON_WIDTH_SHIFT);
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if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
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mtk_dsi_cphy_enable_cmdq_6byte();
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}
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static void mtk_dsi_start(void)
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@ -339,6 +365,7 @@ static enum cb_err mtk_dsi_cmdq(enum mipi_dsi_transaction type, const u8 *data,
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}
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write32(&dsi0->dsi_cmdq_size, 1 + DIV_ROUND_UP(len, 4));
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}
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setbits32(&dsi0->dsi_cmdq_size, CMDQ_SIZE_SEL);
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mtk_dsi_start();
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@ -351,7 +378,7 @@ static enum cb_err mtk_dsi_cmdq(enum mipi_dsi_transaction type, const u8 *data,
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return CB_SUCCESS;
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}
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static void mtk_dsi_reset_dphy(void)
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static void mtk_dsi_reset_phy(void)
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{
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setbits32(&dsi0->dsi_con_ctrl, DPHY_RESET);
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clrbits32(&dsi0->dsi_con_ctrl, DPHY_RESET);
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@ -362,18 +389,28 @@ int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
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{
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u32 data_rate;
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u32 bits_per_pixel = mtk_dsi_get_bits_per_pixel(format);
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bool is_cphy = !!(mode_flags & MIPI_DSI_MODE_CPHY);
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data_rate = mtk_dsi_get_data_rate(bits_per_pixel, lanes, edid);
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if (!CONFIG(MEDIATEK_DSI_CPHY) && is_cphy) {
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printk(BIOS_ERR, "%s: Board is built without C-PHY interface support. "
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"Please check Kconfig MEDIATEK_DSI_CPHY.\n", __func__);
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return -1;
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}
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data_rate = mtk_dsi_get_data_rate(bits_per_pixel, lanes, edid, is_cphy);
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if (!data_rate)
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return -1;
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mtk_dsi_configure_mipi_tx(data_rate, lanes);
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mtk_dsi_configure_mipi_tx(data_rate, lanes, is_cphy);
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mtk_dsi_reset();
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struct mtk_phy_timing phy_timing;
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mtk_dsi_phy_timing(data_rate, &phy_timing);
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struct mtk_phy_timing phy_timing = {};
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if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
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mtk_dsi_cphy_timing(data_rate, &phy_timing);
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else
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mtk_dsi_dphy_timing(data_rate, &phy_timing);
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mtk_dsi_rxtx_control(mode_flags, lanes);
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mdelay(1);
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mtk_dsi_reset_dphy();
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mtk_dsi_reset_phy();
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mtk_dsi_clk_hs_mode_disable();
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mtk_dsi_config_vdo_timing(mode_flags, format, lanes, edid, &phy_timing);
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mtk_dsi_clk_hs_mode_enable();
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@ -1,7 +1,69 @@
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/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
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#include <assert.h>
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#include <delay.h>
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#include <device/mmio.h>
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#include <soc/dsi.h>
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#include <soc/pll.h>
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void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy)
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{
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unsigned int txdiv0;
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u64 pcw;
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if (data_rate >= 2000 * MHz) {
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txdiv0 = 0;
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} else if (data_rate >= 1000 * MHz) {
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txdiv0 = 1;
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} else if (data_rate >= 500 * MHz) {
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txdiv0 = 2;
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} else if (data_rate > 250 * MHz) {
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/* (data_rate == 250MHz) is a special case that should go to the
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else-block below (txdiv0 = 4) */
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txdiv0 = 3;
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} else {
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/* MIN = 125 */
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assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ * MHz);
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txdiv0 = 4;
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}
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if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
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mtk_dsi_cphy_lane_sel_setting();
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clrbits32(&mipi_tx->pll_con4, BIT(11) | BIT(10));
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setbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_PWR_ON);
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udelay(30);
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clrbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_ISO_EN);
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pcw = (u64)data_rate * (1 << txdiv0);
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pcw <<= 24;
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pcw /= CLK26M_HZ;
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write32(&mipi_tx->pll_con0, pcw);
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clrsetbits32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8);
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udelay(30);
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setbits32(&mipi_tx->pll_con1, RG_DSI_PLL_EN);
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/* BG_LPF_EN / BG_CORE_EN */
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write32(&mipi_tx->lane_con, 0x3FFF0180);
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udelay(40);
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write32(&mipi_tx->lane_con, 0x3FFF00C0);
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if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
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mtk_dsi_cphy_enable();
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/* Switch OFF each Lane */
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clrbits32(&mipi_tx->d0_sw_ctl_en, DSI_SW_CTL_EN);
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clrbits32(&mipi_tx->d1_sw_ctl_en, DSI_SW_CTL_EN);
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clrbits32(&mipi_tx->d2_sw_ctl_en, DSI_SW_CTL_EN);
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clrbits32(&mipi_tx->d3_sw_ctl_en, DSI_SW_CTL_EN);
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clrbits32(&mipi_tx->ck_sw_ctl_en, DSI_SW_CTL_EN);
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||||
|
||||
if (CONFIG(MEDIATEK_DSI_CPHY) && is_cphy)
|
||||
mtk_dsi_cphy_disable_ck_mode();
|
||||
else
|
||||
mtk_dsi_dphy_disable_ck_mode();
|
||||
}
|
||||
|
||||
void mtk_dsi_reset(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -43,6 +43,8 @@ enum {
|
|||
MIPI_DSI_MODE_LPM = BIT(11),
|
||||
/* dsi per line's data end same time on all lanes */
|
||||
MIPI_DSI_MODE_LINE_END = BIT(12),
|
||||
/* mipi is in CPHY mode */
|
||||
MIPI_DSI_MODE_CPHY = BIT(13),
|
||||
};
|
||||
|
||||
static struct dsi_regs *const dsi0 = (void *)DSI0_BASE;
|
||||
|
|
@ -57,6 +59,11 @@ enum {
|
|||
DSI_BUSY = BIT(31),
|
||||
};
|
||||
|
||||
/* DSI_CMD_TYPE1_HS */
|
||||
enum {
|
||||
CMD_CPHY_6BYTE_EN = BIT(18),
|
||||
};
|
||||
|
||||
/* DSI_CON_CTRL */
|
||||
enum {
|
||||
DSI_RESET = BIT(0),
|
||||
|
|
@ -103,6 +110,7 @@ enum {
|
|||
/* DSI_CMDQ_SIZE */
|
||||
enum {
|
||||
CMDQ_SIZE = 0x3f,
|
||||
CMDQ_SIZE_SEL = BIT(15),
|
||||
};
|
||||
|
||||
/* DSI_PHY_LCCON */
|
||||
|
|
@ -192,13 +200,25 @@ struct mtk_phy_timing {
|
|||
|
||||
/* Functions that each SOC should provide. */
|
||||
void mtk_dsi_reset(void);
|
||||
void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes);
|
||||
|
||||
/* Functions as weak no-ops that can be overridden. */
|
||||
void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing);
|
||||
|
||||
/* Public API provided in common/dsi_common.c */
|
||||
int mtk_dsi_bpp_from_format(u32 format);
|
||||
/*
|
||||
* Public API provided in common/dsi_common.c, common/dsi_v1.c, and
|
||||
* common/mtk_mipi_{c/d}phy.c
|
||||
*/
|
||||
void mtk_dsi_cphy_enable(void);
|
||||
void mtk_dsi_cphy_enable_cmdq_6byte(void);
|
||||
void mtk_dsi_cphy_lane_sel_setting(void);
|
||||
void mtk_dsi_cphy_timing(u32 data_rate, struct mtk_phy_timing *timing);
|
||||
void mtk_dsi_cphy_vdo_timing(const u32 lanes, const struct edid *edid,
|
||||
const struct mtk_phy_timing *phy_timing,
|
||||
const u32 bytes_per_pixel, const u32 hbp, const u32 hfp,
|
||||
s32 *hbp_byte, s32 *hfp_byte, u32 *hsync_active_byte);
|
||||
void mtk_dsi_cphy_disable_ck_mode(void);
|
||||
void mtk_dsi_dphy_disable_ck_mode(void);
|
||||
void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy);
|
||||
int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, const struct edid *edid,
|
||||
const u8 *init_commands);
|
||||
|
||||
|
|
|
|||
|
|
@ -31,24 +31,29 @@ struct dsi_regs {
|
|||
u32 dsi_bllp_wc;
|
||||
u32 dsi_cmdq_size;
|
||||
u32 dsi_hstx_cklp_wc;
|
||||
u8 reserved2[156];
|
||||
u8 reserved2[4];
|
||||
u32 dsi_cmd_type1_hs;
|
||||
u8 reserved3[148];
|
||||
u32 dsi_phy_lccon;
|
||||
u32 dsi_phy_ld0con;
|
||||
u8 reserved3[4];
|
||||
u8 reserved4[4];
|
||||
u32 dsi_phy_timecon0;
|
||||
u32 dsi_phy_timecon1;
|
||||
u32 dsi_phy_timecon2;
|
||||
u32 dsi_phy_timecon3;
|
||||
u8 reserved4[16];
|
||||
u32 dsi_cphy_con0;
|
||||
u8 reserved5[12];
|
||||
u32 dsi_vm_cmd_con;
|
||||
u8 reserved5[92];
|
||||
u8 reserved6[92];
|
||||
u32 dsi_force_commit; /* Available since MT8183 */
|
||||
u8 reserved6[2924];
|
||||
u8 reserved7[2924];
|
||||
u32 dsi_cmdq[128];
|
||||
};
|
||||
|
||||
check_member(dsi_regs, dsi_cmd_type1_hs, 0x6c);
|
||||
check_member(dsi_regs, dsi_phy_lccon, 0x104);
|
||||
check_member(dsi_regs, dsi_phy_timecon3, 0x11c);
|
||||
check_member(dsi_regs, dsi_cphy_con0, 0x120);
|
||||
check_member(dsi_regs, dsi_vm_cmd_con, 0x130);
|
||||
check_member(dsi_regs, dsi_force_commit, 0x190);
|
||||
check_member(dsi_regs, dsi_cmdq, 0xd00);
|
||||
|
|
|
|||
112
src/soc/mediatek/common/mtk_mipi_cphy.c
Normal file
112
src/soc/mediatek/common/mtk_mipi_cphy.c
Normal file
|
|
@ -0,0 +1,112 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
|
||||
|
||||
#include <assert.h>
|
||||
#include <device/mmio.h>
|
||||
#include <delay.h>
|
||||
#include <soc/dsi.h>
|
||||
#include <soc/pll.h>
|
||||
#include <types.h>
|
||||
|
||||
#define DE_EMPHASIS_EN BIT(9)
|
||||
#define DSI_CPHY_EN BIT(3)
|
||||
#define DSI_HSTX_LDO_REF_SEL GENMASK(9, 6)
|
||||
#define HFP_HS_EN BIT(31)
|
||||
|
||||
#define MIPITX_CPHY_LANE_SEL0_SETTING 0x65432101
|
||||
#define MIPITX_CPHY_LANE_SEL1_SETTING 0x24210987
|
||||
#define MIPITX_CPHY_LANE_SEL2_SETTING 0x68543102
|
||||
#define MIPITX_CPHY_LANE_SEL3_SETTING 0x00000007
|
||||
|
||||
void mtk_dsi_cphy_lane_sel_setting(void)
|
||||
{
|
||||
write32(&mipi_tx->phy_sel[0], MIPITX_CPHY_LANE_SEL0_SETTING);
|
||||
write32(&mipi_tx->phy_sel[1], MIPITX_CPHY_LANE_SEL1_SETTING);
|
||||
write32(&mipi_tx->phy_sel[2], MIPITX_CPHY_LANE_SEL2_SETTING);
|
||||
write32(&mipi_tx->phy_sel[3], MIPITX_CPHY_LANE_SEL3_SETTING);
|
||||
}
|
||||
|
||||
void mtk_dsi_cphy_enable(void)
|
||||
{
|
||||
setbits32(&mipi_tx->lane_con, DSI_CPHY_EN);
|
||||
}
|
||||
|
||||
void mtk_dsi_cphy_disable_ck_mode(void)
|
||||
{
|
||||
clrsetbits32(&mipi_tx->voltage_sel, DSI_HSTX_LDO_REF_SEL, 0xF << 6);
|
||||
clrbits32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN);
|
||||
setbits32(&mipi_tx->lane_con, DE_EMPHASIS_EN);
|
||||
}
|
||||
|
||||
void mtk_dsi_cphy_enable_cmdq_6byte(void)
|
||||
{
|
||||
clrbits32(&dsi0->dsi_cmd_type1_hs, CMD_CPHY_6BYTE_EN);
|
||||
}
|
||||
|
||||
void mtk_dsi_cphy_timing(u32 data_rate, struct mtk_phy_timing *timing)
|
||||
{
|
||||
u32 cycle_time, value;
|
||||
|
||||
data_rate = data_rate / MHz;
|
||||
cycle_time = 7000 / data_rate;
|
||||
printk(BIOS_INFO, "cycle_time = %d data_rate= %d\n", cycle_time, data_rate);
|
||||
/* spec. lpx > 50ns */
|
||||
timing->lpx = DIV_ROUND_UP(75, cycle_time);
|
||||
/* spec. 38ns < hs_prpr < 95ns */
|
||||
timing->da_hs_prepare = DIV_ROUND_UP(64, cycle_time);
|
||||
/* spec. 7ui < hs_zero(prebegin) < 448ui */
|
||||
timing->da_hs_zero = 48;
|
||||
/* spec. 7ui < hs_trail(post) < 224ui */
|
||||
timing->da_hs_trail = 32;
|
||||
|
||||
/* spec. ta_get = 5*lpx */
|
||||
timing->ta_get = 5 * timing->lpx;
|
||||
/* spec. ta_sure = 1.5*lpx */
|
||||
timing->ta_sure = 3 * timing->lpx / 2;
|
||||
/* spec. ta_go = 4*lpx */
|
||||
timing->ta_go = 4 * timing->lpx;
|
||||
/* spec. da_hs_exit > 100ns */
|
||||
timing->da_hs_exit = DIV_ROUND_UP(125, cycle_time);
|
||||
|
||||
/* Allow board-specific tuning. */
|
||||
mtk_dsi_override_phy_timing(timing);
|
||||
|
||||
value = timing->lpx | timing->da_hs_prepare << 8 |
|
||||
timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
|
||||
write32(&dsi0->dsi_phy_timecon0, value);
|
||||
|
||||
value = timing->ta_go | timing->ta_sure << 8 |
|
||||
timing->ta_get << 16 | timing->da_hs_exit << 24;
|
||||
write32(&dsi0->dsi_phy_timecon1, value);
|
||||
|
||||
write32(&dsi0->dsi_cphy_con0, 0x012C0003);
|
||||
write32(&dsi0->dsi_bllp_wc, 16 * 3);
|
||||
}
|
||||
|
||||
void mtk_dsi_cphy_vdo_timing(const u32 lanes,
|
||||
const struct edid *edid,
|
||||
const struct mtk_phy_timing *phy_timing,
|
||||
const u32 bytes_per_pixel,
|
||||
const u32 hbp,
|
||||
const u32 hfp,
|
||||
s32 *hbp_byte,
|
||||
s32 *hfp_byte,
|
||||
u32 *hsync_active_byte)
|
||||
{
|
||||
s32 active_byte, phy_cycle, phy_trail, tmp;
|
||||
u32 hs_vb_ps_wc, ps_wc, data_phy_cycles;
|
||||
|
||||
active_byte = edid->mode.hspw * bytes_per_pixel - 10 * lanes - 26;
|
||||
*hsync_active_byte = MAX(4, active_byte);
|
||||
active_byte = hbp * bytes_per_pixel - 12 * lanes - 26;
|
||||
*hbp_byte = MAX(4, active_byte);
|
||||
data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare +
|
||||
phy_timing->da_hs_zero + phy_timing->da_hs_exit + 5;
|
||||
phy_cycle = 8 * lanes + 28 + 2 * data_phy_cycles * lanes;
|
||||
phy_trail = 2 * (phy_timing->da_hs_trail + 1) * lanes - 6 * lanes - 14;
|
||||
tmp = hfp * bytes_per_pixel - phy_cycle;
|
||||
*hfp_byte = MIN(MAX(8, tmp), phy_trail);
|
||||
ps_wc = edid->mode.ha * bytes_per_pixel;
|
||||
hs_vb_ps_wc = ps_wc - (phy_timing->lpx + phy_timing->da_hs_exit +
|
||||
phy_timing->da_hs_prepare + phy_timing->da_hs_zero + 2) * lanes;
|
||||
*hfp_byte |= hs_vb_ps_wc << 16 | HFP_HS_EN;
|
||||
}
|
||||
|
|
@ -1,63 +1,9 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <assert.h>
|
||||
#include <device/mmio.h>
|
||||
#include <delay.h>
|
||||
#include <soc/dsi.h>
|
||||
#include <soc/pll.h>
|
||||
#include <types.h>
|
||||
|
||||
void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes)
|
||||
void mtk_dsi_dphy_disable_ck_mode(void)
|
||||
{
|
||||
unsigned int txdiv0, txdiv1;
|
||||
u64 pcw;
|
||||
|
||||
if (data_rate >= 2000 * MHz) {
|
||||
txdiv0 = 0;
|
||||
txdiv1 = 0;
|
||||
} else if (data_rate >= 1000 * MHz) {
|
||||
txdiv0 = 1;
|
||||
txdiv1 = 0;
|
||||
} else if (data_rate >= 500 * MHz) {
|
||||
txdiv0 = 2;
|
||||
txdiv1 = 0;
|
||||
} else if (data_rate > 250 * MHz) {
|
||||
/* (data_rate == 250MHz) is a special case that should go to the
|
||||
else-block below (txdiv0 = 4) */
|
||||
txdiv0 = 3;
|
||||
txdiv1 = 0;
|
||||
} else {
|
||||
/* MIN = 125 */
|
||||
assert(data_rate >= MTK_DSI_DATA_RATE_MIN_MHZ * MHz);
|
||||
txdiv0 = 4;
|
||||
txdiv1 = 0;
|
||||
}
|
||||
|
||||
clrbits32(&mipi_tx->pll_con4, BIT(11) | BIT(10));
|
||||
setbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_PWR_ON);
|
||||
udelay(30);
|
||||
clrbits32(&mipi_tx->pll_pwr, AD_DSI_PLL_SDM_ISO_EN);
|
||||
|
||||
pcw = (u64)data_rate * (1 << txdiv0) * (1 << txdiv1);
|
||||
pcw <<= 24;
|
||||
pcw /= CLK26M_HZ;
|
||||
|
||||
write32(&mipi_tx->pll_con0, pcw);
|
||||
clrsetbits32(&mipi_tx->pll_con1, RG_DSI_PLL_POSDIV, txdiv0 << 8);
|
||||
udelay(30);
|
||||
setbits32(&mipi_tx->pll_con1, RG_DSI_PLL_EN);
|
||||
|
||||
/* BG_LPF_EN / BG_CORE_EN */
|
||||
write32(&mipi_tx->lane_con, 0x3fff0180);
|
||||
udelay(40);
|
||||
write32(&mipi_tx->lane_con, 0x3fff00c0);
|
||||
|
||||
/* Switch OFF each Lane */
|
||||
clrbits32(&mipi_tx->d0_sw_ctl_en, DSI_SW_CTL_EN);
|
||||
clrbits32(&mipi_tx->d1_sw_ctl_en, DSI_SW_CTL_EN);
|
||||
clrbits32(&mipi_tx->d2_sw_ctl_en, DSI_SW_CTL_EN);
|
||||
clrbits32(&mipi_tx->d3_sw_ctl_en, DSI_SW_CTL_EN);
|
||||
clrbits32(&mipi_tx->ck_sw_ctl_en, DSI_SW_CTL_EN);
|
||||
|
||||
setbits32(&mipi_tx->ck_ckmode_en, DSI_CK_CKMODE_EN);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
#include <soc/dsi.h>
|
||||
#include <timer.h>
|
||||
|
||||
void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes)
|
||||
void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes, bool is_cphy)
|
||||
{
|
||||
u32 txdiv0, txdiv1;
|
||||
u64 pcw;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue