Swathi Tamilselvan 2f9b4ad6a5 soc/qualcomm/x1p42100: Add DFSR table configuration support ... Add support to configure DFSR table, introduce qupv3_clock_v2 structure to calculate register addresses for serial engines 2 and 3. Update CBCR registers to use the new structure for QUPv3 clock enablement. BUG=b:444617760 TEST=Create an image.serial.bin and ensure it boots on X1P42100. Dump DFSR registers for corresponding QUP and check if values are updated properly into correct register address. Change-Id: Ibd7e4bf121bd99130336047a50ed70d4cbec2234 Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90145 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>		2025-11-25 16:47:20 +00:00
..
amd	soc/amd/cezanne: Add SOC_AMD_RENOIR as a Cezanne variant	2025-11-20 17:39:08 +00:00
cavium
example/min86
ibm/power9	soc/power9/rom_media.c: find CBFS in PNOR	2025-08-28 20:14:01 +00:00
intel	soc/intel/common/block/rtc/rtc.c: control Top Swap via CMOS option	2025-11-25 16:47:10 +00:00
mediatek	soc/mediatek/mt8196/booker: Refactor CMO property clearing with loop	2025-11-24 04:32:34 +00:00
nvidia
qualcomm	soc/qualcomm/x1p42100: Add DFSR table configuration support	2025-11-25 16:47:20 +00:00
rockchip
samsung
sifive
ti
ucb/riscv	soc/riscv/ucb: Switch to FDT parsing to get memory size	2025-02-26 17:11:09 +00:00
xilinx	soc/xilinx/zynq7000: Initial Xilinx Zynq 7000 SoC bringup	2025-01-23 00:41:01 +00:00