Make the name more generic since it applies to both haswell
and broadwell chips.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I46aa67e144deb79bd5348a4104da7dc0d0889329
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198918
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Pull together all the used register definitions from the
cpu/northbridge/southbridge chip.h files into one structure
for the broadwell SOC.
Add a chip.c file that contains the main chip_operations
structure as well as a shared pci_operations structure that
can be used by other ramstage drivers.
The chip broadwell_enable function handles different bus types
and splits the work out to the right subsystem.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I42ceed278b3cd5c46c2384c3f6528246a2193cc8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198917
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These registers are in MCHBAR so they should live in the
system agent header instead of the CPU header.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I037e5b74943bca8e04fa65986c7e421f144da96a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198916
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a reset_system() function that is used in romstage and ramstage
code and a broadwell/reset.h header for it.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I4f96f0506a1147382b46b3540ffd5f520894fdc5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198915
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the ACPI related defines and function prototypes to a new
header at broadwell/acpi.h.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: Id3e3e92d535613e2a8ffbf6b39d07d1ac231e9bd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198914
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the formatting throughout the ACPI code to be consistent
with the rest of the coreboot codebase
Also remove unused variables and clean up some comments
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I6fbd14f9faefa21cc4e17a6a509d00299c222fdd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198913
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use the newly provided broadwell/iomap.h to get the base addresses
that need to be defined in ACPI.
Add device resource consumption ResourceTemplate() for these
base addresses.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I8dffd7e7d0722868c5477bc4b2b9d4621406a223
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198912
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since the broadwell code only supports the "low power" variant
there is no need to check for it in the ACPI code.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I5347750cd627bcb4e4f5fce587df931725f417df
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198911
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The GPIO controller device has been moved to separate gpio.asl
so remove the code from serialio.asl.
The SerialIO devices no longer have enable status reported in a
separate SSDT so remove the External defines.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: If06b609475dd2fc32a0333c9e38fc456c6116756
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198910
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The CTDP related methods are moved from systemagent.asl to a
new ctdp.asl file.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I4d0df9af27501b925ec0f12daeb5980903a637d6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198898
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Removed unused variables from the ACPI NVS region and separate
out the variables used to communicate SerialIO base address and
enable status.
Some now unused ACPI methods in globalnvs.asl have been removed.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I20e26c7ebfb25975f315c3e41e67fee3f50df539
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198897
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the
architecture specific to that stage i.e. we will have CONFIG_ARCH variables for
each of the three stages. This allows us to have an SOC with any combination of
architectures and thus every stage can be made to run on a completely different
architecture independent of others. Thus, bootblock can have an x86 arch whereas
romstage and ramstage can have arm32 and arm64 arch respectively. These stage
specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain
and compiler flags for every stage.
These options can be considered as either arch or modes eg: x86 running in
different modes or ARM having different arch types (v4, v7, v8). We have got rid
of the original CONFIG_ARCH option completely as every stage can have any
architecture of its own. Thus, almost all the components of coreboot are
identified as being part of one of the three stages (bootblock, romstage or
ramstage). The components which cannot be classified as such e.g. smm, rmodules
can have their own compiler toolset which is for now set to *_i386. Hence, all
special classes are treated in a similar way and the compiler toolset is defined
using create_class_compiler defined in Makefile.
In order to meet these requirements, changes have been made to CC, LD, OBJCOPY
and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others.
Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the
toolsets are defined using create_class_compiler.
Few additional macros have been introduced to identify the class to be used at
various points, e.g.: CC_$(class) derives the $(class) part from the name of
the stage being compiled.
We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and
COREBOOT_LINKER as they do not make any sense for coreboot as a whole. All these
attributes are associated with each of the stages.
BUG=None
BRANCH=None
TEST=Compiled successfully for all mainboard/google boards. Image booted
successfully on link, rambi and nyan.
Change-Id: I10d36ff950712756fb16dcb4d315924d177846b5
Reviewed-on: https://chromium-review.googlesource.com/195574
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Remove all the common Makefile rules like coreboot.pre, coreboot.pre1 and others
from arch level Makefile.inc to top level Makefile.inc.
Also, organize Makefile.inc at arch level into per-stage rules and variables.
BUG=None
BRANCH=None
TEST=Compiled successfully. Image booted successfully on link,nyan and rambi.
Change-Id: I22f5ef692b740f84d73071534732286e809f3bc4
Reviewed-on: https://chromium-review.googlesource.com/195446
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
CONFIG_ARCH is a property of the cpu or soc rather than a property of the
board. Hence, move ARCH_* from every single board to respective cpu or soc
Kconfigs. Also update abuild to ignore ARCH_ from mainboards.
BUG=None
BRANCH=None
TEST=Compiled successfully for all mainboard/google boards. Successfully booted
link image.
Change-Id: I42323ac33c236d26654a26b591378781aeecabd4
Reviewed-on: https://chromium-review.googlesource.com/195350
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Add the header file used to communicate information to the intel
reference code binaries. This is shared directly with the PEI
wrapper in the binary. A broadwell specific function is defined
to fill out platform specific information and a function prototype
is provided for the mainboard to implement.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: Ib3254cbd0c1a890ffb716cab551f68b6201812d2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198743
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This broadwell implementation will support Haswell ULT in
addition to broadwell CPUs. Add the latest available microcode
for the broadwell C0 and D0 parts as well as Haswell ULT.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I1beb71e0e28af3508e2260751b6fdfe47d53d90d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198742
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Put some generic ramstage function prototypes into the a new
header at broadwell/ramstage.h for easy access. Some of these
functions are defined in a later commit.
This file also contains the exported 'broadwell_pci_ops' that can
be used by ramstage drivers and is defined in broadwell/chip.c
BUG=chrome-os-partner:28234
TEST=None
Change-Id: Idfa1f9ab46d1bf4efbefea46548f97653786e6f1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198741
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Put all the exported romstage functions (that are not also defined
in ramstage) into broadwell/romstage.h for easy access.
Some of the stuff in this file is not used yet but will be part of
a later commit.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I69db33ba95afa3c3868c7c09ed53ed80567d17f4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198740
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Create a new header at broadwell/msr.h that contains the various
defined MSRs for this CPU generation. The MSRs from cpu.h and
the ones defined in smmrelocate.c are in this new header.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: Id0652d0f7e4bad0992c057b530fc5e05e2dfabb2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198739
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This puts all the SMM related information into one location
instead of being split across several headers.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: If4782d37f28b325ff76dd8efa560840d4e1da276
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198738
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This header will allow the broadwell code to access specific
devices without worrying about the differences in device_t
type between romstage/smm and ram stage.
These new devices will be used in subsequent commits that clean
up the broadwell drivers.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I457c39b6a5262a6ad50034e711de4e8174815d8d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198737
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of having various defined base addresses in different
headers put them all in one well defined location. The names
are changed to be more consistent with baytrail implementation.
Some defines are for early temporary base addresses, a few of
which are taken from Kconfig variables and are set here in order
to be consistent with the ones that are not defined in Kconfig.
The code will be changed to use the new defines in subsequent
commits.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I315d8c6f4188244bc86342e8c5dce60924653c58
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198736
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the smbus romstage/ramstage related code into smbus_common.c
and split out the smbus related defines/prototypes from pch.h
to broadwell/smbus.h.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: Ide534ee8d13868fb3ab0a277c958b862c5dfeeb7
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198735
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Pull the IOBP related defines and functions from pch.c/pch.h
into separate iobp.c/iobp.h.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: Ic510360c14594f4fd46249c238ac851372045893
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198734
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
LPAE (large physical address extension) is not available on this SOC
core, do not enable it.
BUG=chrome-os-partner:27784
TEST=coreboot still comes up on AP148
Change-Id: I9e9ad1aeaf613f04987c0c306a574085042d0e7b
Signed-off-by: Deepa Dinamani <deepad@codeaurora.com>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198023
Reviewed-by: deepa dinamani <deepad@quicinc.com>
There is redundancy in terms of use of init_timer. We have a Kconfig option to
decide whether a board has init_timer as well as we use stub for init_timer in
places where we do not have any init_timer defined. Thus, removing the Kconfig
option. Henceforth, all boards that do not have init_timer functionality can
include include a stub_timer if required.
BUG=None
BRANCH=None
TEST=Compiled successfully for all mainboard/google/ boards as well as all the
other boards that were compiling fine before this change using abuild still
compile fine. No additional errors introduced because of this change
Change-Id: Iaffec9ce92107e55d65cc7c9f317feeeba700242
Reviewed-on: https://chromium-review.googlesource.com/195250
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Patch to rename coreboot_ram stage to ramstage. This is done in order to provide
consistency with other stage names(bootblock, romstage) and to allow any
Makefile rule generalization. (Required for patches to be submitted later)
CQ-DEPEND=CL:195101
BUG=None
BRANCH=None
TEST=Compiled successfully for all boards under mainboard/google/. Image booted
successfully on link board
Change-Id: I3e2495fc6a5cc91695ae04ffb438dd4ac265be64
Reviewed-on: https://chromium-review.googlesource.com/195059
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Move the XHCI and EHCI related register/bit defines into a separate
header file at broadwell/ehci.h and broadwell/xhci.h
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I24df90c797ebdc5dee1fe84ed57c565c5360dd1c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198554
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the GPIO related register/bit defines into a separate header
file at broadwell/gpio.h. Also clean up the existing file to remove
the "low-power" variant differences since this is now the only
supported GPIO interface for broadwell.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I8c50bf368753e40a90940e387d7dc79dc5568f55
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198553
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the LPC related register/bit defines into a separate header
file at broadwell/lpc.h
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I42acc57e436524103500f05bdc2c8f7a02b3a918
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198552
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the SerialIO related register/bit defines into a separate header
file at broadwell/serialio.h
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I84fea5fd0b2c82f37e7aa025ed0188e0bf19c411
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198551
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Split the SPI related register/bit defines into a separate header
at broadwell/spi.h
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I6d675ede9f3d25a47761543dbf1e18e15e8f63e8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198550
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the SATA related register/bit defines into a separate header
file at broadwell/sata.h
BUG=chrome-os-partner:28234
TEST=None
Change-Id: Ia92439533d99def96316bab4898d38388e52c4dd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198429
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Split out defines for RCBA related registers/bits into a separate
header file in broadwell/rcba.h.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I070317015b546bb8a641e9a12279e3f86152ca66
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198428
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Various register/bit defines for power management offsets
in PMBASE are split into a separate header together with
the prototypes for pmutil helper functions.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I3d79e288b79641d8c4b4c8d10ed122b0c5c7e143
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198427
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use the same copyright string and license formatting in
every file in the soc/intel/broadwell directory.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: Ibfa9f1f10ad0e2410d200f7120d07a793a2bbfb2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198426
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The haswell and lynxpoint code will form the starting point for
broadwell support but it will be heavily reworked to fit into
a unified soc directory.
For now just copy in the raw starting sources.
BUG=chrome-os-partner:28234
TEST=None
Change-Id: I013c5c95e839a27979da8b6ebbee290529ae3279
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198425
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When a watchdog reset happens, the SOC will reset but other parts of the
system might not. That puts the machine in a funny state and may prevent it
from booting properly.
BUG=chrome-os-partner:28559
TEST=Built for nyan, nyan_big and nyan_blaze. Booted normally, through EC
reset, software reset ("reboot" command from the terminal), and through watch
dog reset. Verified that the new code only triggered during the watchdog reset
and that the system rebooted and was able to boot without going into recovery
mode unnecessarily.
BRANCH=nyan
Change-Id: Id92411c928344547fcd97e45063e4aff52d2e9e8
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/198582
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
When a watchdog reset happens, the SOC will reset but other parts of the
system might not. In order to detect those situations we can check the
rst_status register in the PMC.
BUG=chrome-os-partner:28559
TEST=With this and a change which uses the new function in the nyan boards,
built for nyan, nyan_big and nyan_blaze. Booted normally, through EC reset,
software reset ("reboot" command from the terminal), and through watch dog
reset. Verified that the new code only triggered during the watchdog reset and
that the system rebooted and was able to boot without going into recovery mode
unnecessarily.
BRANCH=nyan
Change-Id: I7430768baa0304d4ec8524957a9cc37078ac5a71
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/198581
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Added the empty function clear_recovery_mode_switch (weak)
Problem:
If GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC is set,
the following will happen:
1. Boot device in recovery mode with Esc + F3 + Pwr.
2. Turn device off with Pwr button.
3. Turn device on with Pwr button.
Device still boots to recovery screen with
recovery_reason:0x02 recovery button pressed.
If GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC isn't set,
turning the device off and on again
with the Pwr button does a normal boot.
Solution:
Unconditionally clear the recovery flag.
BUG=chromium:279607
BRANCH=TOT
TEST=Compile OK.
Change-Id: Ie1e3251a6db12e75e385220e9d3791078393b1bf
Signed-off-by: Sheng-Liang Song <ssl@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/197780
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Sheng-liang Song <ssl@google.com>
Tested-by: Sheng-liang Song <ssl@google.com>
The original sdram-hynix-2GB-792.inc was just copied from nyan
bct file. This change updates the cfg file for Hynix 2GB, 792MHz
DRAM based on the data generated by t124_emc_reg_tool.
BUG=none
BRANCH=blaze
TEST=emerged coreboot, booted successfully into kernel.
Change-Id: I9534b4df6d35193179de124309df12ed830098a0
Signed-off-by: Ken Chang <kenc@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/197660
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
All what's needed apart from configuring the feature is to provide a
function which would report the top of DRAM address.
BUG=chrome-os-partner:27784
TEST=manual
. with all other patches applied, the image proceeds all the way to
trying to download 'fallback/payload'.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Change-Id: Ifa586964c931976df1dff354066670463f8e9ee3
Reviewed-on: https://chromium-review.googlesource.com/197897
Length arguments for VbExTpmSendReceive have type uint32_t but it calls function
which expects size_t. This change converts uint32_t to size_t on call and
size_t to uint32_t on return.
BUG=None
BRANCH=None
TEST=Booted Nyan Big to Linux
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I1971488baae2d060c0cddec7749461c91602a4f9
Reviewed-on: https://chromium-review.googlesource.com/198016
This is a fix for the 'Lost arb' we're seeing on Nyan* during
reboot stress testing. It occurs when we are slamming the
default PMIC registers with pmic_write_reg().
Currently, I've only captured this a few times, and the bus
clear seemed to work, as the PMIC writes continued (where
they'd hang the system before bus clear) for a couple of regs,
then it hangs hard, no messages, no 2nd lost arb, etc. So
I've added code to the PMIC write function that will reset the
SoC if any I2C error occurs. That seems to recover OK, i.e. on
the next reboot the PMIC writes all go thru, boot is OK, kernel
loads, etc.
BUG=chrome-os-partner:28323
BRANCH=nyan
TEST=Tested on nyan. Built for nyan and nyan_big.
Change-Id: I1ac5e3023ae22c015105b7f0fb7849663b4aa982
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/197732
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
