Duncan Laurie 49d7a023f3 broadwell: Clean up broadwell/systemagent.h ... - Remove unused chipset type defines - Remove unused/undefined registers in MCHBAR/DMIBAR/EPBAR - Remove unused function prototypes - Fix MCHBAR macros to use MCH_BASE_ADDRESS - MRC cache defines/prototypes are in soc/intel/common BUG=chrome-os-partner:28234 TEST=None Change-Id: I9477f61d4756f787022245e5c134c0250f20dbe3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198920 Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2014-05-09 21:53:41 +00:00
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arch	coreboot: Introduce stage-specific architecture for coreboot	2014-05-09 04:41:47 +00:00
console	ipq8064: make UART driver work in bootblock	2014-04-25 01:51:13 +00:00
cpu	coreboot: Introduce stage-specific architecture for coreboot	2014-05-09 04:41:47 +00:00
device	coreboot: Introduce stage-specific architecture for coreboot	2014-05-09 04:41:47 +00:00
drivers	coreboot ARM: Get rid of HAVE_INIT_TIMER config option	2014-05-07 23:30:33 +00:00
ec	chromeos: Unconditionally clear the EC recovery request	2014-05-07 03:33:49 +00:00
include	coreboot: Introduce stage-specific architecture for coreboot	2014-05-09 04:41:47 +00:00
lib	coreboot: Introduce stage-specific architecture for coreboot	2014-05-09 04:41:47 +00:00
mainboard	coreboot: Introduce stage-specific architecture for coreboot	2014-05-09 04:41:47 +00:00
northbridge	coreboot: Rename coreboot_ram stage to ramstage	2014-05-07 23:30:23 +00:00
soc	broadwell: Clean up broadwell/systemagent.h	2014-05-09 21:53:41 +00:00
southbridge	coreboot: Rename coreboot_ram stage to ramstage	2014-05-07 23:30:23 +00:00
superio	pnp: Allow setting of misc register 0xf4 in device tree	2013-12-20 00:37:38 +00:00
vendorcode	coreboot: Introduce stage-specific architecture for coreboot	2014-05-09 04:41:47 +00:00
Kconfig	coreboot: Introduce stage-specific architecture for coreboot	2014-05-09 04:41:47 +00:00