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coreboot: Rename coreboot_ram stage to ramstage

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Patch to rename coreboot_ram stage to ramstage. This is done in order to provide
consistency with other stage names(bootblock, romstage) and to allow any
Makefile rule generalization. (Required for patches to be submitted later)

CQ-DEPEND=CL:195101
BUG=None
BRANCH=None
TEST=Compiled successfully for all boards under mainboard/google/. Image booted
successfully on link board

Change-Id: I3e2495fc6a5cc91695ae04ffb438dd4ac265be64
Reviewed-on: https://chromium-review.googlesource.com/195059
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Furquan Shaikh 2014-04-15 20:48:40 -07:00 • committed by chrome-internal-fetch
commit d9558852c4
35 changed files with 56 additions and 56 deletions
Download patch file Download diff file Expand all files Collapse all files

2
Makefile.inc
View file

@ -322,7 +322,7 @@ clean-abuild:
rm -rf coreboot-builds
clean-for-update-target:
rm -f $(obj)/coreboot_ram* $(obj)/coreboot.romstage $(obj)/coreboot.pre* $(obj)/coreboot.bootblock $(obj)/coreboot.a
rm -f $(obj)/ramstage* $(obj)/coreboot.romstage $(obj)/coreboot.pre* $(obj)/coreboot.bootblock $(obj)/coreboot.a
rm -rf $(obj)/bootblock* $(obj)/romstage* $(obj)/location.*
rm -f $(obj)/option_table.* $(obj)/crt0.S $(obj)/ldscript
rm -f $(obj)/mainboard/$(MAINBOARDDIR)/static.c $(obj)/mainboard/$(MAINBOARDDIR)/config.py $(obj)/mainboard/$(MAINBOARDDIR)/static.dot

2
src/Kconfig
View file

@ -173,7 +173,7 @@ config INCLUDE_CONFIG_FILE
Name Offset Type Size
cmos_layout.bin 0x0 cmos layout 1159
fallback/romstage 0x4c0 stage 339756
fallback/coreboot_ram 0x53440 stage 186664
fallback/ramstage 0x53440 stage 186664
fallback/payload 0x80dc0 payload 51526
config 0x8d740 raw 3324
(empty) 0x8e480 null 3610440

14
src/arch/aarch64/Makefile.inc
View file

@ -61,10 +61,10 @@ $(obj)/coreboot.pre: $(CBFSTOOL)
mv $(obj)/coreboot.rom $@
endif
$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE)
$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE)
@printf " CBFS $(subst $(obj)/,,$(@))\n"
cp $(obj)/coreboot.pre $@.tmp
$(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/coreboot_ram.elf -n $(CONFIG_CBFS_PREFIX)/coreboot_ram -c $(CBFS_COMPRESS_FLAG)
$(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/ramstage.elf -n $(CONFIG_CBFS_PREFIX)/ramstage -c $(CBFS_COMPRESS_FLAG)
ifeq ($(CONFIG_PAYLOAD_NONE),y)
@printf " PAYLOAD none (as specified by user)\n"
endif
@ -105,17 +105,17 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug
mv $@.tmp $@
################################################################################
# Build the coreboot_ram (stage 2)
# Build the ramstage (stage 2)
$(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/aarch64/coreboot_ram.ld
$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(src)/arch/aarch64/ramstage.ld
@printf " CC $(subst $(obj)/,,$(@))\n"
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
$(LD) -m armelf_linux_eabi -o $@ -L$(obj) $< -T $(src)/arch/aarch64/coreboot_ram.ld
$(LD) -m armelf_linux_eabi -o $@ -L$(obj) $< -T $(src)/arch/aarch64/ramstage.ld
else
$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/aarch64/coreboot_ram.ld $<
$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/aarch64/ramstage.ld $<
endif
$(objgenerated)/coreboot_ram.o: $(stages_o) $$(ramstage-objs) $(LIBGCC_FILE_NAME)
$(objgenerated)/ramstage.o: $(stages_o) $$(ramstage-objs) $(LIBGCC_FILE_NAME)
@printf " CC $(subst $(obj)/,,$(@))\n"
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
$(LD) -m -m armelf_linux_eabi -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) --end-group

2
src/arch/aarch64/coreboot_ram.ld → src/arch/aarch64/ramstage.ld
View file

@ -17,7 +17,7 @@
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
* 2005.12 yhlu add coreboot_ram cross the vga font buffer handling
* 2005.12 yhlu add ramstage cross the vga font buffer handling
*/
/* We use ELF as output format. So that we can debug the code in some form. */

2
src/arch/aarch64/romstage.ld
View file

@ -16,7 +16,7 @@
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
* 2005.12 yhlu add coreboot_ram cross the vga font buffer handling
* 2005.12 yhlu add ramstage cross the vga font buffer handling
*/
/* We use ELF as output format. So that we can debug the code in some form. */

10
src/arch/arm/Makefile.inc
View file

@ -132,10 +132,10 @@ $(obj)/coreboot.pre1: $(CBFSTOOL)
mv $(obj)/coreboot.rom $@
endif
$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(VBOOT_STUB)
$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(VBOOT_STUB)
@printf " CBFS $(subst $(obj)/,,$(@))\n"
cp $(obj)/coreboot.pre $@.tmp
$(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/coreboot_ram.elf -n $(CONFIG_CBFS_PREFIX)/coreboot_ram -c $(CBFS_COMPRESS_FLAG)
$(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/ramstage.elf -n $(CONFIG_CBFS_PREFIX)/ramstage -c $(CBFS_COMPRESS_FLAG)
ifeq ($(CONFIG_PAYLOAD_NONE),y)
@printf " PAYLOAD none (as specified by user)\n"
endif
@ -182,12 +182,12 @@ endif
################################################################################
# Build the ramstage
$(objcbfs)/coreboot_ram.debug: $$(ramstage-objs) $(src)/arch/arm/coreboot_ram.ld $(obj)/ldoptions
$(objcbfs)/ramstage.debug: $$(ramstage-objs) $(src)/arch/arm/ramstage.ld $(obj)/ldoptions
@printf " CC $(subst $(obj)/,,$(@))\n"
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
$(LD) -nostdlib -m armelf_linux_eabi --gc-sections -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --start-group $(ramstage-objs) --end-group -T $(src)/arch/arm/coreboot_ram.ld
$(LD) -nostdlib -m armelf_linux_eabi --gc-sections -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --start-group $(ramstage-objs) --end-group -T $(src)/arch/arm/ramstage.ld
else
$(CC) $(CFLAGS) -nostdlib -Wl,--gc-sections -static -o $@ -L$(obj) -Wl,--start-group $(ramstage-objs) -Wl,--end-group -T $(src)/arch/arm/coreboot_ram.ld
$(CC) $(CFLAGS) -nostdlib -Wl,--gc-sections -static -o $@ -L$(obj) -Wl,--start-group $(ramstage-objs) -Wl,--end-group -T $(src)/arch/arm/ramstage.ld
endif
################################################################################

2
src/arch/arm/armv4/bootblock.S
View file

@ -84,6 +84,6 @@ ENDPROC(_start)
.Stack:
.word CONFIG_STACK_TOP
.align 2
/* create this size the same way we do in coreboot_ram.ld: top-bottom */
/* create this size the same way we do in ramstage.ld: top-bottom */
.Stack_size:
.word CONFIG_STACK_TOP - CONFIG_STACK_BOTTOM

2
src/arch/arm/armv7/bootblock.S
View file

@ -98,6 +98,6 @@ ENDPROC(_thumb_start)
.Stack:
.word CONFIG_STACK_TOP
.align 2
/* create this size the same way we do in coreboot_ram.ld: top-bottom */
/* create this size the same way we do in ramstage.ld: top-bottom */
.Stack_size:
.word CONFIG_STACK_TOP - CONFIG_STACK_BOTTOM

2
src/arch/arm/coreboot_ram.ld → src/arch/arm/ramstage.ld
View file

@ -16,7 +16,7 @@
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
* 2005.12 yhlu add coreboot_ram cross the vga font buffer handling
* 2005.12 yhlu add ramstage cross the vga font buffer handling
*/
/* We use ELF as output format. So that we can debug the code in some form. */

2
src/arch/arm/romstage.ld
View file

@ -16,7 +16,7 @@
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
* 2005.12 yhlu add coreboot_ram cross the vga font buffer handling
* 2005.12 yhlu add ramstage cross the vga font buffer handling
*/
/* We use ELF as output format. So that we can debug the code in some form. */

18
src/arch/x86/Makefile.inc
View file

@ -80,10 +80,10 @@ $(REFCODE_BLOB): $(RMODTOOL)
$(RMODTOOL) -i $(CONFIG_REFCODE_BLOB_FILE) -o $@
endif
$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) $$(VBOOT_STUB) $(REFCODE_BLOB)
$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) $$(VBOOT_STUB) $(REFCODE_BLOB)
@printf " CBFS $(subst $(obj)/,,$(@))\n"
cp $(obj)/coreboot.pre $@.tmp
$(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/coreboot_ram.elf -n $(CONFIG_CBFS_PREFIX)/coreboot_ram -c $(CBFS_COMPRESS_FLAG)
$(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/ramstage.elf -n $(CONFIG_CBFS_PREFIX)/ramstage -c $(CBFS_COMPRESS_FLAG)
ifeq ($(CONFIG_PAYLOAD_NONE),y)
@printf " PAYLOAD none (as specified by user)\n"
endif
@ -170,29 +170,29 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug
mv $@.tmp $@
################################################################################
# Build the coreboot_ram (stage 2)
# Build the ramstage (stage 2)
ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y)
$(eval $(call rmodule_link,$(objcbfs)/coreboot_ram.debug, $(objgenerated)/coreboot_ram.o, $(CONFIG_HEAP_SIZE)))
$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE)))
# The rmodule_link defintion creates an elf file with .rmod extension.
$(objcbfs)/coreboot_ram.elf: $(objcbfs)/coreboot_ram.debug.rmod
$(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
cp $< $@
else
$(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld
$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(src)/arch/x86/ramstage.ld
@printf " CC $(subst $(obj)/,,$(@))\n"
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
$(LD) -m elf_i386 -o $@ -L$(obj) $< -T $(src)/arch/x86/coreboot_ram.ld
$(LD) -m elf_i386 -o $@ -L$(obj) $< -T $(src)/arch/x86/ramstage.ld
else
$(CC) $(CFLAGS) -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/coreboot_ram.ld $<
$(CC) $(CFLAGS) -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/ramstage.ld $<
endif
endif
$(objgenerated)/coreboot_ram.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME)
$(objgenerated)/ramstage.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME)
@printf " CC $(subst $(obj)/,,$(@))\n"
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
$(LD) -m elf_i386 -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) --end-group

2
src/arch/x86/lib/cbfs_and_run.c
View file

@ -42,5 +42,5 @@ static void cbfs_and_run_core(const char *filename)
void asmlinkage copy_and_run(void)
{
cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram");
cbfs_and_run_core(CONFIG_CBFS_PREFIX "/ramstage");
}

2
src/arch/x86/coreboot_ram.ld → src/arch/x86/ramstage.ld
View file

@ -16,7 +16,7 @@
/*
* Written by Johan Rydberg, based on work by Daniel Kahlin.
* Rewritten by Eric Biederman
* 2005.12 yhlu add coreboot_ram cross the vga font buffer handling
* 2005.12 yhlu add ramstage cross the vga font buffer handling
*/
/* We use ELF as output format. So that we can debug the code in some form. */

2
src/cpu/amd/car/disable_cache_as_ram.c
View file

@ -36,7 +36,7 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
#if CONFIG_DCACHE_RAM_SIZE > 0x8000
wrmsr(MTRRfix4K_C0000_MSR, msr);
#endif
/* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/
/* disable fixed mtrr from now on, it will be enabled by ramstage again*/
msr = rdmsr(SYSCFG_MSR);
msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn);

2
src/cpu/amd/car/post_cache_as_ram.c
View file

@ -164,7 +164,7 @@ static void post_cache_as_ram(void)
set_sysinfo_in_ram(1); // So other core0 could start to train mem
/*copy and execute coreboot_ram */
/*copy and execute ramstage */
copy_and_run();
/* We will not return */

4
src/cpu/amd/geode_lx/msrinit.c
View file

@ -42,11 +42,11 @@ static const msrinit_t msr_table[] =
/* Pre-setup access to memory above 1Mb. Here we set up about 500Mb of memory.
* It doesn't really matter in fact how much, however, because the only usage
* of this extended memory will be to host the coreboot_ram stage at RAMBASE,
* of this extended memory will be to host the ramstage stage at RAMBASE,
* currently 1Mb.
* These registers will be set to their correct value by the Northbridge init code.
*
* WARNING: if coreboot_ram could not be loaded, these registers are probably
* WARNING: if ramstage could not be loaded, these registers are probably
* incorrectly set here. You may comment the following two lines and set RAMBASE
* to 0x4000 to revert to the previous behavior for LX-boards.
*/

2
src/cpu/intel/model_206ax/cache_as_ram.inc
View file

@ -248,7 +248,7 @@ before_romstage:
post_code(0x38)
/* Enable Write Back and Speculative Reads for the first MB
* and coreboot_ram.
* and ramstage.
*/
movl $MTRRphysBase_MSR(0), %ecx
movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax

2
src/cpu/x86/pae/pgtbl.c
View file

@ -1,5 +1,5 @@
/*
2005.12 yhlu add coreboot_ram cross the vga font buffer handling
2005.12 yhlu add ramstage cross the vga font buffer handling
*/
#include <console/console.h>

2
src/lib/rmodule.ld
View file

@ -34,7 +34,7 @@ SECTIONS
/* The driver sections are to allow linking coreboot's
* ramstage with the rmodule linker. Any changes made in
* coreboot_ram.ld should be made here as well. */
* ramstage.ld should be made here as well. */
console_drivers = .;
*(.rodata.console_drivers)
econsole_drivers = . ;

4
src/lib/selfboot.c
View file

@ -38,7 +38,7 @@
#define MAX_ADDR -1UL
#endif
/* from coreboot_ram.ld: */
/* from ramstage.ld: */
extern unsigned char _ram_seg;
extern unsigned char _eram_seg;
@ -488,7 +488,7 @@ static int load_self_segments(
/* Zero the extra bytes */
memset(middle, 0, end - middle);
}
/* Copy the data that's outside the area that shadows coreboot_ram */
/* Copy the data that's outside the area that shadows ramstage */
printk(BIOS_DEBUG, "dest %p, end %p, bouncebuffer %lx\n", dest, end, bounce_buffer);
if ((unsigned long)end > bounce_buffer) {
if ((unsigned long)dest < bounce_buffer) {

2
src/mainboard/emulation/foundation-armv8/romstage.c
View file

@ -23,7 +23,7 @@ void main(void)
console_init();
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
stage_exit(entry);
}

2
src/mainboard/emulation/qemu-armv7/romstage.c
View file

@ -23,7 +23,7 @@ void main(void)
console_init();
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
stage_exit(entry);
}

2
src/mainboard/google/daisy/romstage.c
View file

@ -196,7 +196,7 @@ void main(void)
timestamp_add(TS_AFTER_INITRAM, after_dram_time );
#endif
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
#if CONFIG_COLLECT_TIMESTAMPS
timestamp_add_now(TS_END_ROMSTAGE);

2
src/mainboard/google/nyan/romstage.c
View file

@ -232,7 +232,7 @@ static void __attribute__((noinline)) romstage(void)
timestamp_add(TS_START_COPYRAM, timestamp_get());
void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
"fallback/coreboot_ram");
"fallback/ramstage");
timestamp_add(TS_END_COPYRAM, timestamp_get());
stage_exit(entry);

2
src/mainboard/google/nyan_big/romstage.c
View file

@ -232,7 +232,7 @@ static void __attribute__((noinline)) romstage(void)
timestamp_add(TS_START_COPYRAM, timestamp_get());
void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
"fallback/coreboot_ram");
"fallback/ramstage");
timestamp_add(TS_END_COPYRAM, timestamp_get());
stage_exit(entry);

2
src/mainboard/google/nyan_blaze/romstage.c
View file

@ -232,7 +232,7 @@ static void __attribute__((noinline)) romstage(void)
timestamp_add(TS_START_COPYRAM, timestamp_get());
void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
"fallback/coreboot_ram");
"fallback/ramstage");
timestamp_add(TS_END_COPYRAM, timestamp_get());
stage_exit(entry);

2
src/mainboard/google/peach_pit/romstage.c
View file

@ -292,7 +292,7 @@ void main(void)
timestamp_add(TS_AFTER_INITRAM, after_dram_time );
#endif
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
simple_spi_test();
#if CONFIG_COLLECT_TIMESTAMPS

2
src/mainboard/google/storm/romstage.c
View file

@ -25,6 +25,6 @@ void main(void)
{
void *entry;
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
stage_exit(entry);
}

2
src/northbridge/amd/amdfam10/amdfam10.h
View file

@ -1033,7 +1033,7 @@ struct nodes_info_t {
u32 up_planes; // down planes will be [up_planes, planes)
} __attribute__((packed));
/* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and coreboot_ram stage. and coreboot_ram may be running at 64bit later.*/
/* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and ramstage stage. and ramstage may be running at 64bit later.*/
#if !CONFIG_AMDMCT
//#define MEM_CS_COPY 1

2
src/northbridge/amd/amdk8/get_sblk_pci1234.c
View file

@ -80,7 +80,7 @@ unsigned node_link_to_bus(unsigned node, unsigned link)
* pci1234[0] will record the south bridge link and bus range
* pci1234[i] will record HT chain i.
*
* For example, on the Tyan S2885 coreboot_ram will put the AMD8151 chain (HT
* For example, on the Tyan S2885 ramstage will put the AMD8151 chain (HT
* link 0) into the register 0xE0, and the AMD8131/8111 HT chain into the
* register 0xE4.
*

2
src/soc/nvidia/tegra124/bootblock_asm.S
View file

@ -84,6 +84,6 @@ ENDPROC(_start)
.Stack:
.word CONFIG_STACK_TOP
.align 2
/* create this size the same way we do in coreboot_ram.ld: top-bottom */
/* create this size the same way we do in ramstage.ld: top-bottom */
.Stack_size:
.word CONFIG_STACK_TOP - CONFIG_STACK_BOTTOM

2
src/southbridge/broadcom/bcm5785/early_setup.c
View file

@ -177,7 +177,7 @@ static void bcm5785_early_setup(void)
byte |= (1<<0); // SATA enable
pci_write_config8(dev, 0x84, byte);
// WDT and cf9 for later in coreboot_ram to call hard_reset
// WDT and cf9 for later in ramstage to call hard_reset
bcm5785_enable_wdt_port_cf9();
bcm5785_enable_msg();

2
src/vendorcode/google/chromeos/vboot_loader.c
View file

@ -314,7 +314,7 @@ static void vboot_load_ramstage(struct vboot_handoff *vboot_handoff,
const struct firmware_component *fwc;
struct rmod_stage_load rmod_load = {
.cbmem_id = CBMEM_ID_RAMSTAGE,
.name = CONFIG_CBFS_PREFIX "/coreboot_ram",
.name = CONFIG_CBFS_PREFIX "/ramstage",
};
if (CONFIG_VBOOT_RAMSTAGE_INDEX >= MAX_PARSED_FW_COMPONENTS) {

2
util/genprof/README
View file

@ -26,6 +26,6 @@ that.
Great use is:
make
./genprof /tmp/yourlog ; gprof ../../build/coreboot_ram | ./gprof2dot.py -e0 -n0 | dot -Tpng -o output.png
./genprof /tmp/yourlog ; gprof ../../build/ramstage | ./gprof2dot.py -e0 -n0 | dot -Tpng -o output.png
Which generates a PNG with a call graph.

4
util/genprof/log2dress
View file

@ -10,9 +10,9 @@ A=`echo $line | cut -c 1`
if [ "$A" = '~' ] ; then
FROM=`echo $line | tr \~ \( | tr \) \( | awk -F\( '{print $3}'`
TO=`echo $line | tr \~ \( | tr \) \(|awk -F\( '{print $2}'`
addr2line -e ../../build/cbfs/fallback/coreboot_ram.debug "$FROM" | tr -d "\n"
addr2line -e ../../build/cbfs/fallback/ramstage.debug "$FROM" | tr -d "\n"
echo -n " calls "
addr2line -e ../../build/cbfs/fallback/coreboot_ram.debug "$TO"
addr2line -e ../../build/cbfs/fallback/ramstage.debug "$TO"
else
echo "$line"
fi