tegra124: Add a utility function to read the cause of the most recent reset.

When a watchdog reset happens, the SOC will reset but other parts of the
system might not. In order to detect those situations we can check the
rst_status register in the PMC.

BUG=chrome-os-partner:28559
TEST=With this and a change which uses the new function in the nyan boards,
built for nyan, nyan_big and nyan_blaze. Booted normally, through EC reset,
software reset ("reboot" command from the terminal), and through watch dog
reset. Verified that the new code only triggered during the watchdog reset and
that the system rebooted and was able to boot without going into recovery mode
unnecessarily.
BRANCH=nyan

Change-Id: I7430768baa0304d4ec8524957a9cc37078ac5a71
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/198581
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>

src/soc/nvidia/tegra124/Makefile.inc

@@ -28,6 +28,7 @@ romstage-y += early_display.c
 romstage-y += dma.c
 romstage-y += i2c.c
 romstage-y += monotonic_timer.c
+romstage-y += power.c
 romstage-y += sdram.c
 romstage-y += sdram_lp0.c
 romstage-y += spi.c

src/soc/nvidia/tegra124/power.c

@@ -85,3 +85,8 @@ void power_ungate_cpu(void)
 	// Ungate power to CPU0 in the fast cluster.
 	power_ungate_partition(POWER_PARTID_CE0);
 }
+
+int power_reset_status(void)
+{
+	return read32(&pmc->rst_status) & 0x7;
+}

src/soc/nvidia/tegra124/power.h

@@ -26,4 +26,15 @@ void power_enable_cpu_rail(void);
 
 void power_ungate_cpu(void);
 
+// power_reset_status returns one of the following possible sources for the
+// most recent reset.
+enum {
+	POWER_RESET_POR = 0,
+	POWER_RESET_WATCHDOG = 1,
+	POWER_RESET_SENSOR = 2,
+	POWER_RESET_SW_MAIN = 3,
+	POWER_RESET_LP0 = 4
+};
+int power_reset_status(void);
+
 #endif	/* __SOC_NVIDIA_TEGRA124_POWER_H__ */