The busy check is only supported on Fam 17h Picasso and Raven Ridge.
On other platforms the register might not exist and the bits always
read as ones. This prevents the PSP SMI handler from accessing
the SPI flash.
TEST: Ensured that the code does not block on 1Ah platforms.
Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: I063b7cd66a5058ae558ad36e4a7dd89a48f718a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
Add support for limiting SATA interface speed through the FSP parameter
'SataSpeedLimit'. This is useful for mainboards with physical design
constraints that require operating at lower speeds than what the
controller and drives support.
The implementation adds a new chip config option that mainboards can
set in their devicetree to control this behavior.
Change-Id: Ib0a058d006b752975c57851f2418a4e94b3bfcca
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88951
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up to the USB ACPI driver and enable the generation of ACPI code
for enabled USB devices.
Change-Id: I53fc73046e4b107064fa8c3c617ba6d9b807b71d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83211
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
GNR-AP public FSP
- https://github.com/intel/FSP/tree/master/BirchStreamFspBinPkg/ap
GNR-SP public FSP
- https://github.com/intel/FSP/tree/master/BirchStreamFspBinPkg/sp
GNR mainboards will by default use public FSP bin and headers.
If needing to use site-local FSP bin and headers, apply below
settings in the defconfig (use beechnutcity CRB as example),
CONFIG_FSP_USE_REPO=n
CONFIG_ADD_FSP_BINARIES=y
CONFIG_FSP_T_FILE="site-local/beechnutcity/Server_T.fd"
CONFIG_FSP_M_FILE="site-local/beechnutcity/Server_M.fd"
CONFIG_FSP_S_FILE="site-local/beechnutcity/Server_S.fd"
CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/
graniterapids/sp/"
TEST=Build and boot on intel/avenuecity CRB
TEST=Build and boot on intel/beechnutcity CRB
Change-Id: I88701316e21ec4737539294d17926aa0abe8c1fd
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88898
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Hancockc <hancock.chang@mitaccomputing.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Schumi Chu
Reviewed-by: Wilson-MiTACComputing <wilson.chien@mitaccomputing.com>
Reviewed-by: Mark Chang <mark.chang@mitaccomputing.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Granite Rapids SoC has 2 SKUs, a.k.a. GNR-AP and GNR-SP, which
use different FSP headers/binaries. Add Kconfig items to support
these SKU types.
Change-Id: Ie3a2d603f0a2c303e8f3c0911598742fbc25d73a
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88897
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Wilson-MiTACComputing <wilson.chien@mitaccomputing.com>
Reviewed-by: Mark Chang <mark.chang@mitaccomputing.com>
Reviewed-by: Schumi Chu
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Increase the CBFS cache in the memory layout of MediaTek Chromebook SoCs
to allow larger payloads like LinuxBoot to be loaded correctly.
TEST=Build and boot coreboot with LinuxBoot payload for
Google/Cherry/Tomato.
Change-Id: I4ce15e04cc19612ef1eed0fa0674ef8a7fd21fbe
Signed-off-by: Ingo Reitz <9l@9lo.re>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88916
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
The memlayout.ld for X1P42100 was copied from a previous SoC and
lacked clear documentation about the platform's specific memory
organization.
This commit adds a detailed ASCII art diagram that provides a visual
representation of the complete memory map. The diagram clarifies the
locations of all major regions, such as AOPSRAM, SSRAM, BSRAM, SHRM,
and the various DRAM segments, which greatly improves the clarity and
maintainability of the linker script.
TEST=Builds successfully for x1p42100.
Change-Id: Ia1714f8da25a22a13f5960d056df33463dd99f31
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88783
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CPR image is required by Qclib for PMIC initialization. This patch adds
support to pack and load the CPR binary, reserves memory for CPR
settings in the memory layout and adds CPR entry in if_table which
is passed to Qclib.
TEST=1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified using CPR load log from coreboot.
```
[INFO ] CBFS: Found 'fallback/cpr' @0xa3900 size 0x46d in mcache
@0x1485e340
[INFO ] VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not
supported for secdata_kernel v0, return 0
[INFO ] VB2:vb2_digest_init() 1133 bytes, hash algo 2, HW acceleration
forbidden
[INFO ] CBFS: Found 'fallback/shrm_meta' @0xebb80 size 0xb0d in mcache
@0x1485e7c0
```
Change-Id: I58161a1d05222c84e077ada1024db50440e783f1
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88870
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CPR image is required by Qclib for PMIC initialization. This patch
adds support to declare cpr_settings region and create CBFS prefix
for CPR.
Change-Id: Ia92717715eacaf05d33db040d99cf81d8d288111
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88869
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
In the scenario of suspend, when the SPM firmware attempts to turn off
the VDDQ and VMDDR power supplies, the command sent is rejected by PMIF,
resulting in a system hang. The reason is that SPM simultaneously wrote
two registers (two bytes), while the original configuration only allowed
reading or writing one byte at a time.
Modify the maximum number of bytes that an SPMI user can read or write
in a single operation to meet the requirement of reading or writing 16
bits at once.
BUG=b:420874944
BRANCH=skywalker
TEST=2-byte R/W passed; suspend-resume verified successfully.
Change-Id: I46ace45564328c46ab340b74d73e3574957e36ef
Signed-off-by: Niklaus Liu <niklaus.liu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88790
Reviewed-by: Vince Liu <vince-wl.liu@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Niklaus Liu <niklaus.liu@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Some eDP panels assert HPD (Hot Plug Detect) after panel VCC is enabled,
typically around 200ms. To reduce boot time, this commit replaces the
original fixed 200ms delay with polling for the HPD status, shortening
the waiting period to approximately 70ms.
Once the HPD pin is detected high, an additional delay of around 1ms is
introduced to ensure the AUX channel is ready for EDID reading.
BUG=b:434574691,b:439535227,b:439476647
BRANCH=none
TEST=Check firmware display on Navi and Skywalker
Signed-off-by: Bincai Liu <bincai.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: I6702c79416700b44d4bfbc763b6fc6003feb69b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88864
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
The alignment for several memory regions in the linker script was
specified using numeric values like `4096` or the hexadecimal `0x1000`.
Replace these values with the more readable `4K` shorthand. This change
improves consistency within the file and has no functional impact on
the generated binary.
TEST=Build and boot google/quenbi.
Change-Id: I28fdf3714d96f5e68a615d1550cf47d975ab5685
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The `SSRAM_START/END`, `BSRAM_START/END`, and `AOPSRAM_START/END`
macros were redefined across multiple Qualcomm SoC `memlayout.ld` files.
To reduce code duplication and improve maintainability, this commit
moves these common macros into the shared `<soc/memlayout.h>` header
part of the Qualcomm common code.
The SoC-specific linker scripts are updated to remove the local
definitions.
TEST=Built for all affected SoCs (qcs405, sc7180, sc7280, x1p42100)
Change-Id: I8638b8e03e1e51f57b7e91a072f3d9cdb4ec6200
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88782
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the common Qualcomm SoC include path to the qcs405 Makefile.
This allows the SoC-specific code to use shared headers located in
`src/soc/qualcomm/common/include`, promoting better code reuse and
organization.
TEST=Build for qcs405 target successfully.
Change-Id: Ie4bc9f3a4fc259adcdc4107c92aab0cb5c8676c1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit refactors how the CBMEM top address is determined. Instead
of using a hardcoded value, the CBMEM top address is now starts at
offset `_dram_smem`.
Note: CBMEM region grows from top to bottom hence, starting cbmem_top
at offset `_dram_smem` won't override the SMEM reserved range.
The hardcoded value is problematic as it overrides the SMEM reserved
range and resulted into the boot halt.
The changes include:
- cbmem.c: The cbmem_top_chipset() function is updated to return the
address of the `_dram_smem` linker symbol plus its size.
This refactoring removes a magic number from the code, improving
readability, maintainability, and consistency with how other memory
regions are handled.
BUG=b:437948495
TEST=Able to ensure booting google/quenbi till kernel w/o
abrupt shutdown.
```
[DEBUG] CBMEM:
[DEBUG] IMD: root @ 0xff7ff000 254 entries.
[DEBUG] IMD: root @ 0xff7fec00 62 entries.
```
Change-Id: Idb6a8a47f38d873c6ad4f0d995e77e657cc00ac0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit refactors the DRAM memory layout to reserve additional
regions critical for platform functionality and debugging. It
consolidates several CPUCP-related memory areas and adds new
reservations for Ramdump and Shared Memory.
- Ramdump and Shared Memory: New reserved regions, dram_ramdump and
dram_smem, are added to protect memory used for crash dumps and
inter-processor communication.
- CPUCP Optimization: The individual NCC, CPUCP, and CPUCP-DTS regions
are consolidated into a single, contiguous dram_cpucp region from
0x80A00000 to 0x815A0000. This simplifies the memory map and
optimizes resource allocation.
Reserving these regions is crucial to prevent other bootloader stages
or the kernel from overwriting critical firmware data, which could lead
to unexpected behavior or system instability.
BUG=b:437948495
TEST=Able to ensure booting google/quenbi till kernel.
Change-Id: I80f6d288dd054a34a1e60736c8b14f072559c1ac
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88779
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates the x1p42100 platform to support a dynamic memory
layout for DRAM. This is a crucial step toward supporting different
board variants with varying memory capacities.
The changes involve:
- ramstage build: The mmu.c source file is now included in the ramstage
build, providing the necessary functions to configure the Memory
Management Unit (MMU) for fragmented memory regions.
- Linker Script (memlayout.ld): The dram_space_1 and dram_space_2
regions are statically defined with their maximum possible sizes.
- SoC Initialization (soc.c): The soc_read_resources function is
refactored to use a new helper function, qc_get_soc_dram_space_config,
to retrieve a list of available DRAM regions. It then iterates through
this list to dynamically register each memory region with ram_range.
This replaces the previous static ram_range call with a more flexible
approach that can handle fragmented memory maps. Reserved regions are
also updated to use a dynamic index.
This refactoring allows the system to correctly handle memory maps for
devices with more than 2GB of DRAM, which was a limitation of the
previous static configuration.
TEST=Able to build and boot google/quenbi w/ 16GB of DRAM (using
DDR_SPACE and DDR_SPACE_1 regions).
Change-Id: If94644110272713f77db5a0dd6d23ec0798a15f0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88753
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Stating with Qualcomm X1P42100 SoC generation, the DRAM memory map is
not expected to be contiguous (unlike previous generations) therefore,
the memory map could be something like this.
1. Assume hardware design has 4GB of DRAM then the memory map would
look like:
- DDR_SPACE (2 GB) : 0x80000000 - 0x100000000
- DDR_SPACE_1 (2 GB) : 0x880000000 - 0x900000000
2. Assume hardware design has 16GB of DRAM then the memory map would
look like:
- DDR_SPACE (2 GB) : 0x80000000 - 0x100000000
- DDR_SPACE_1 (14 GB) : 0x880000000 - 0x400000000
3. Assume hardware design has 64GB of DRAM then the memory map would
look like:
- DDR_SPACE (2 GB) : 0x80000000 - 0x100000000
- DDR_SPACE_1 (30 GB) : 0x880000000 - 0x1000000000
- DDR_SPACE_2 (32 GB) : 0x8800000000 - 0x9000000000
This commit introduces logic to handle systems with fragmented DRAM
configurations. Previously, the Memory Management Unit (MMU) was
configured assuming a single, contiguous block of DRAM.
This change extends the MMU setup to properly configure multiple,
non-contiguous DRAM regions.
The changes include:
- Declaring dram_space_1 and dram_space_2 as optional regions, allowing
the dynamic allocation for these DRAM ranges based on DRAM capacity of
the platform.
- Introduce `qc_get_soc_dram_space_config` function that takes care of
DRAM based resource splitting as per `_dram`, `_dram_space_1` and
`_dram_space_2` region limit.
- Modifying qc_mmu_dram_config_post_dram_init() to check for these
optional regions and configure them individually. This ensures all
available DRAM is correctly mapped and accessible to the system.
This approach improves flexibility and allows coreboot to support a
wider range of Qualcomm platforms with different memory layouts.
TEST=Able to boot google/quenbi to OS.
Change-Id: If3788f4c77535f9a5e47ad2034ab9a8e0fe85b51
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88752
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit refactors the qc_mmu_dram_config_post_dram_init function
to remove the ddr_base parameter. The function can now retrieve the
base address of the DRAM from the ddr_region global variable, which
is already available.
TEST=Able to build and boot google/quenbi.
Change-Id: I97159dee6a035ed3e38cbfca1e44b8e671d15fc1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Rearm and clear functions are called only if a valid crashlog is
present and extracted. If there is no valid crashlog, rearming will
lead to incorrect notification and skipping of the next crashlog event
BUG=b: None
TEST= PMC discovery buffer - rearmed status bit (trig_armed_sts)
MMIO read of Bit position 25 is rearmed status bit
MMIO read of desc_table_addr = (bar_address + offset)
desc_table_addr = 0x9c198000 + 0x1d00 = 0x9c199d00
:1 for cold boot and
:0 for warm boot after manual crash
Change-Id: I42da487abd383567d7945835b738557e2e3fa714
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
After crashlog data is extracted, CPU rearm command is issued to
prepare the crash logging mechanism for future events. Instead of
command and response polling of mailbox, watcher interface which is a
direct MMIO based, low latency control register is used for efficiency.
In PTL, a Crashlog watcher providing control the same way provided by
Crashlog Mailbox Interface used by (mainly) BIOS is used for all CPU
crashlog control requests from BIOS to PUNIT.
BUG=b: None
TEST= Manually trigger crash using command
iotools mmio_write32 (baraddress + watcher offset=0x10) 0x20000000
followed by warm boot, check rearm status - which is 25th bit of
*(bar_address)
Change-Id: I89dd23fad144c1c7122b5536f1ac848ea66ea6b1
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
According to MediaTek, this delay was added in the driver bring-up stage
to mitigate the display garbage issue. Now, the delay can be removed.
BUG=b:434574691
TEST=Check FW screen on Navi
Change-Id: I5408d95be7a4aaf8bb4bb639c319320514c4fd99
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88744
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Meaure the execution time for following eDP functions.
- dptx_check_sinkcap
- dptx_get_edid
- dptx_set_trainingstart
- mtk_edp_init
These dptx_* functions are the primary contributors to the execution
time of mtk_edp_init, which is only called in dev/recovery mode. This
insight can be used for future boot time optimization by breaking down
the eDP initialization process.
TEST=Boot with DEV mode using the boot image without serial console
support.
TEST=cbmem -c|grep "done after"
[INFO ] dptx_check_sinkcap done after 38 msecs
[INFO ] dptx_get_edid done after 294 msecs
[INFO ] dptx_set_trainingstart done after 100 msecs
[INFO ] mtk_edp_init done after 438 msecs
Change-Id: I7aabf3a33b9628f20fe16980033b00de9afc44e6
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
mtk_edp_init is similar in dptx_v1.c and dptx_v2.c. Make mtk_edp_init
common by
1. Extract dptx_set_tx_power_con and dptx_set_26mhz_clock to
edp_power_on.
2. Add dptx_hal_phy_init weak function for the platform which does not
require initialization.
TEST=emerge-cherry coreboot && emerge-rauru coreboot
Change-Id: I686208c6bf8538354fb4fd238755899b0ef8f86b
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The commit adds new memory regions for the CPUCP (CPU Subsystem Control
Processor) and TZ (TrustZone) components to the x1p42100 SoC. This is
necessary to properly reserve the memory used by these firmware
components during boot.
The changes involve:
- Declaring new memory regions dram_cpucp_dtbs, dram_cpucp, dram_tz,
and dram_tz_rem in the symbols_common.h header.
- Defining the base addresses and sizes for these new regions in
memlayout.ld.
Registering these memory ranges as reserved in the soc_read_resources
function in soc.c so that coreboot does not overwrite them.
TEST=Able to load aop firmware while booting google/quenbi without
boot hang.
Change-Id: I1ecbc1e5ea420b7bdd5518612082ca0e14b35f6e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Suggested-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This patch adds support to skip DDR training when valid training data
is available in flash.
The exact size of the training data is passed to ensure accurate hash
computation. A hash is computed on the DDR training data using the
specified size and compared with the stored hash in the header. This
requires passing only the exact training data size to ensure correct
validation.
TEST=Create an image.serial.bin and ensure it boots on X1P42100. Verify
that the DDR training is skipped when valid data is available in flash.
w/o this patch: doing RW_MRC_CACHE update in every boot.
```
[DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'.
[DEBUG] read SPI 0xc1f290 0xf27c: 5010 us, 12390 KB/s, 99.120 Mbps
[DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update.
[DEBUG] MRC: updated 'RW_MRC_CACHE'.
```
w/ this patch: no need to perform RW_MRC_CACHE update.
```
[DEBUG] FMAP: area RW_MRC_CACHE found @ c10000 (65536 bytes)
[DEBUG] read SPI 0xc10024 0xf268: 5016 us, 12371 KB/s, 98.968 Mbps
```
Change-Id: I1a5ad0766ea77b22e6a8cb97c24a90c24629dfd0
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88742
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Updated the memory layout file to include necessary DDR region
reservations for AOP and BL31.
TEST=Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I67b0210dfc563c0a0e8f879b1f41693e1d0e6384
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Introduce a new `SOC_QUALCOMM_HAMOA` Kconfig option and refactor the
Qualcomm SoC build to support Hamoa.
This change prepares the groundwork for Hamoa-based mainboards by:
- Creating a common base: A new `SOC_QUALCOMM_BASE` Kconfig option
is introduced to group configurations shared between Qualcomm SoCs.
- Separating SoC-specific blobs: The build process now dynamically
selects the correct device tree blob (DTB) and display control blob
(DCB) files for Hamoa via a new `DTB_DCB_BLOB_PATH` variable in the
`Makefile.mk`.
- Enabling future mainboards: This allows mainboards built on the Hamoa
SoC to be configured and built within the existing Qualcomm SoC
directory.
BUG=b:437662790
TEST=Able to build and boot google/quenbi.
Change-Id: Ife983495b757fbf06ad96f0ca15fd89bf41c77c0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88737
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit removes the Pmic.bin file from the coreboot filesystem
(CBFS) and the Makefile.mk for the Qualcomm x1p42100 SoC.
The PMIC file is no longer used in the boot process. It's safe to
remove it to reduce the size of the final coreboot image and clean
up the build configuration.
TEST=Able to build and boot google/quenbi.
Change-Id: Iac8e4b32677f36959323a5dd3a5c7f88a6359720
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88736
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change addresses GCC-15 behavior where {0} union initializers only
clear the first member, leaving padding bits uninitialized. The new {}
initializer ensures full union clearing as required by C23.
Change-Id: I1d9b063d8bdd3d2f0b0f67e6c20eb484ff6a5cc5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Crashlog storage and power management in PTL is changed to a unified
and persistent model,removing the need for manual SRAM power-down
commands after crashlog extraction.
Change-Id: I5bea1c816bbb68a4b2b21cc3be6cf118b4282fe7
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88512
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Commit 87c9bb3994 ("soc/intel/adl: Fill in SPD data on both channels
of DDR5 memory") accidentally deleted the function
mem_init_override_channel_mask().
Additionally, skip checking for channel 0 while consuming the channel
disable mask.
BUG=none
TEST=CQ
Change-Id: I6217b2801e88b8ab98b2a3acaa0cb9580b05bb64
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88697
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit introduces a new Kconfig option, UART_BITBANG_TX_DELAY_MS,
to make the UART TX pin stabilization delay configurable.
A default 5ms (CONFIG_UART_BITBANG_TX_DELAY_MS) delay is added in
uart_init() after the TX pin is set high. This addresses an issue
where the initial character sent by the UART could be corrupted due
to the pin not being stable. The delay ensures the line state is
properly established before data transmission begins.
This was found to resolve early boot console corruption on some boards.
The issue is likely a race condition where the first character starts
transmitting before the GPIO output is fully stabilized.
TEST=Able to build and boot google/zombie w/o any junk characters in
AP firmware log.
w/o this patch:
```
�ɍ���щ�����х�ѥ��b����ٕ��Jrrrjjm UuI5�ፕ�ѥ���������ͥ��х�����jm UuI5���ѥ���ፕ�ѥ��m��jm UuI5����ѕ�ѕፕ�ѥ��m��[DEBUG] NCC Frequency bumped to 1.363(GHz)
```
w/ this patch:
```
[NOTE ] coreboot-25.06-78-gfe786406960e-dirty Fri Aug 01 17:12:22 UTC 2025 aarch64 bootblock starting (log level: 8)...
[DEBUG] ARM64: Exception handlers installed.
[DEBUG] ARM64: Testing exception
[DEBUG] ARM64: Done test exception
[DEBUG] Silver Frequency bumped to 1.5168(GHz)
[DEBUG] L3 Frequency bumped to 1.1904(GHz)
```
Change-Id: I33c9ea65aa42d23acf3b89f977d4985569c144e8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88633
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable bootblock compression on the X1p42100 SoC to decrease boot
time by 10-20 ms.
This change helps to reduce the size of the bootblock, allowing it
to be loaded and decompressed faster, which improves overall boot
performance.
TEST=Able to build and boot google/quenbi.
Change-Id: I81cdbec4a05c8abacae39ff208cc0f7469206161
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88626
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It doesn't make sense to use CONFIG_DIMM_SPD_SIZE to determine the
amount of data to read from the SPD, then override that value.
Clean up the mess and simply set the SPD length fror the spd_block
struct to CONFIG_DIMM_SPD_SIZE.
Change-Id: Ifec6cf1f6d7c931131460ea72440aa236590d0b6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88523
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 91a1276d53 ("soc/intel/alderlake: Implement WA for DDR5 DIMM
modules") was added to allow FSP to perform the SPD read for DDR5
modules since coreboot did not properly support reading SPD from
EEPROM for DDR5. The same code was copied for Meteorlake.
Now that DDR5 SPD EEPROM reading has been fixed in commit e9cb352706
("soc/common/smbus: Support reading SPD5 hubs for DDR5"), remove the
now unneeded workaround for DDR5 and use coreboot's SPD read as we
do for all other module types.
Change-Id: I600d8fd480cb84d5dcb679e4f0bdeeaaebfab386
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82733
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch applies commit 0e7cf3d81d ("soc/intel/alderlake: Fix DDR5
channel mapping") to Meteor Lake.
DDR5 memory modules have two separate 32-bit channels (40-bit on ECC
memory modules), and the SPD info refers to one channel: the primary
bus width is 32 (or 40) bits and the "DIMM size" is halved. On Meteor
Lake, there are 2 memory controllers with 4 32-bit channels each for
DDR5. FSP has 16 positions to store SPD data, some of which are only
used with LPDDR4/LPDDR5.
To try to make things less confusing, FSP abstracts the DDR5 channels
so that the configuration works like on DDR4. This is done by copying
each DIMM's SPD data to the other half-channel. Thus, fix the wrapper
parameters for DDR5 accordingly.
Change-Id: I00cd1fba855a50422a68fa662df4ca8ed2c6458d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88636
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 91a1276d53 ("soc/intel/alderlake: Implement WA for DDR5 DIMM
modules") was added to allow FSP to perform the SPD read for DDR5
modules since coreboot did not properly support reading SPD from
EEPROM for DDR5.
Now that DDR5 SPD EEPROM reading has been fixed in commit e9cb352706
("soc/common/smbus: Support reading SPD5 hubs for DDR5"), remove the
now unneeded workaround for DDR5 and use coreboot's SPD read as we
do for all other module types.
Change-Id: I5a92199a7cd2718e9396f0dac8257df40e4f834c
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75284
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Since MT8189G does not support APU, the LDO_VSRAM_OTHERS and BUCK_VCORE
regulators for the APU power domain can be turned off. Disabling these
power supplies reduces overall system power consumption by about 1mW.
BUG=b:420874944,b:421989583,b:423081787
BRANCH=none
TEST=Verified by measuring system current in S3 state before and after
disabling APU power.
Signed-off-by: Niklaus Liu <niklausi.liu@mediatek.corp-partner.google.com>
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Signed-off-by: Zhigang Qin <zhigang.qin@mediatek.corp-partner.google.com>
Change-Id: I4e4eeb575327b554f5837bfc0f6a464ff7a1e228
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Include `stdint.h` in `cpu_id.h` to ensure `u32` is properly defined.
This resolves build errors when files including `cpu_id.h` cannot find
the definition for `u32`.
BUG=b:379008996
BRANCH=none
TEST=build passed
Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com>
Change-Id: If4b41a6eae38470d4d30baeeef50c8b1ebb82033
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88630
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce the disable_progress_bar setting in configuration to allow
disabling the memory training progress bar during firmware
initialization.
BUG=b:418675387
TEST=After setting disable_progress_bar, memory training progress bar
is disabled.
Change-Id: I35e8191df27c0eda634724580514e980bd620136
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
