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soc/qc/x1p42100: Add memory layouts for CPUCP and TZ regions

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The commit adds new memory regions for the CPUCP (CPU Subsystem Control
Processor) and TZ (TrustZone) components to the x1p42100 SoC. This is
necessary to properly reserve the memory used by these firmware
components during boot.

The changes involve:
 - Declaring new memory regions dram_cpucp_dtbs, dram_cpucp, dram_tz,
   and dram_tz_rem in the symbols_common.h header.
 - Defining the base addresses and sizes for these new regions in
   memlayout.ld.

Registering these memory ranges as reserved in the soc_read_resources
function in soc.c so that coreboot does not overwrite them.

TEST=Able to load aop firmware while booting google/quenbi without
boot hang.

Change-Id: I1ecbc1e5ea420b7bdd5518612082ca0e14b35f6e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Suggested-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This commit is contained in:
Subrata Banik 2025-08-12 13:38:20 +05:30
commit e49e8c6355
3 changed files with 15 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

3
src/soc/qualcomm/common/include/soc/symbols_common.h
View file

@ -26,7 +26,10 @@ DECLARE_REGION(dram_modem_extra)
DECLARE_REGION(dram_wlan)
DECLARE_REGION(dram_wpss)
DECLARE_REGION(shrm)
DECLARE_REGION(dram_cpucp_dtbs)
DECLARE_REGION(dram_cpucp)
DECLARE_REGION(dram_modem)
DECLARE_REGION(dram_tz)
DECLARE_REGION(dram_tz_rem)
#endif // _SOC_QUALCOMM_SYMBOLS_COMMON_H_

6
src/soc/qualcomm/x1p42100/memlayout.ld
View file

@ -57,8 +57,12 @@ SECTIONS
REGION(shrm, 0x24040000, 128K , 4K)
DRAM_START(0x80000000)
REGION(dram_aop, 0x81c00000, 0x0a0000, 0x1000)
REGION(dram_cpucp_dtbs, 0x81240000, 0x2000, 0x1000)
REGION(dram_cpucp, 0x81250000, 0x80000, 0x1000)
REGION(dram_aop, 0x81C00000, 0xF780000, 0x1000)
POSTRAM_CBFS_CACHE(0x9F800000, 16M)
RAMSTAGE(0xA0800000, 16M)
REGION(dram_tz, 0xD8000000, 0xD6000, 0x1000)
BL31(0xD80D6000, 1M)
REGION(dram_tz_rem, 0xD81D6000, 0x72EA000, 0x1000)
}

8
src/soc/qualcomm/x1p42100/soc.c
View file

@ -15,7 +15,13 @@ static struct device_operations pci_domain_ops = {
static void soc_read_resources(struct device *dev)
{
ram_range(dev, 0, (uintptr_t)region_offset(ddr_region), region_sz(ddr_region));
reserved_ram_range(dev, 1, (uintptr_t)_dram_aop, REGION_SIZE(dram_aop));
reserved_ram_range(dev, 1, (uintptr_t)_dram_cpucp_dtbs, REGION_SIZE(dram_cpucp_dtbs));
reserved_ram_range(dev, 2, (uintptr_t)_dram_cpucp, REGION_SIZE(dram_cpucp));
reserved_ram_range(dev, 3, (uintptr_t)_dram_tz, REGION_SIZE(dram_tz));
reserved_ram_range(dev, 4, (uintptr_t)_dram_tz_rem, REGION_SIZE(dram_tz_rem));
reserved_ram_range(dev, 5, (uintptr_t)_dram_aop, REGION_SIZE(dram_aop));
}
static void soc_init(struct device *dev)