soc/intel/alderlake: Make SATA speed limit configurable

Add support for limiting SATA interface speed through the FSP parameter
'SataSpeedLimit'. This is useful for mainboards with physical design
constraints that require operating at lower speeds than what the
controller and drives support.

The implementation adds a new chip config option that mainboards can
set in their devicetree to control this behavior.

Change-Id: Ib0a058d006b752975c57851f2418a4e94b3bfcca
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88951
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/alderlake/chip.h

@@ -341,6 +341,12 @@ enum slew_rate {
 	SLEW_FAST_16
 };
 
+enum sata_speed_limit {
+	SATA_DEFAULT,
+	SATA_GEN1,	/* 1.5 Gbps */
+	SATA_GEN2	/* 3.0 Gbps */
+};
+
 struct soc_intel_alderlake_config {
 	/* Common struct containing soc config data required by common code */
 	struct soc_intel_common_config common_soc_config;
@@ -416,6 +422,7 @@ struct soc_intel_alderlake_config {
 	bool sata_salp_support;
 	bool sata_ports_enable[8];
 	bool sata_ports_dev_slp[8];
+	enum sata_speed_limit sata_speed;
 
 	/*
 	 * Enable(0)/Disable(1) SATA Power Optimizer on PCH side.

src/soc/intel/alderlake/fsp_params.c

@@ -778,6 +778,7 @@ static void fill_fsps_sata_params(FSP_S_CONFIG *s_cfg,
 	if (s_cfg->SataEnable) {
 		s_cfg->SataMode = config->sata_mode;
 		s_cfg->SataSalpSupport = config->sata_salp_support;
+		s_cfg->SataSpeedLimit = config->sata_speed;
 		memcpy(s_cfg->SataPortsEnable, config->sata_ports_enable,
 			sizeof(s_cfg->SataPortsEnable));
 		memcpy(s_cfg->SataPortsDevSlp, config->sata_ports_dev_slp,