erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

soc/mediatek: Increase CBFS cache to 8MB in memlayout.ld

Browse source 
Increase the CBFS cache in the memory layout of MediaTek Chromebook SoCs
to allow larger payloads like LinuxBoot to be loaded correctly.

TEST=Build and boot coreboot with LinuxBoot payload for
Google/Cherry/Tomato.

Change-Id: I4ce15e04cc19612ef1eed0fa0674ef8a7fd21fbe
Signed-off-by: Ingo Reitz <9l@9lo.re>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88916
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
This commit is contained in:
Ingo Reitz 2025-08-24 02:42:30 +02:00 • committed by Matt DeVillier
commit 4931b978d9
4 changed files with 8 additions and 8 deletions
Download patch file Download diff file Expand all files Collapse all files

4
src/soc/mediatek/mt8183/memlayout.ld
View file

@ -26,8 +26,8 @@ SECTIONS
DRAM_START(0x40000000)
DRAM_DMA(0x40000000, 1M)
POSTRAM_CBFS_CACHE(0x40100000, 1M)
RAMSTAGE(0x40200000, 2M)
POSTRAM_CBFS_CACHE(0x40100000, 8M)
RAMSTAGE(0x40900000, 2M)
BL31(0x54600000, 0x60000)
}

4
src/soc/mediatek/mt8186/include/soc/memlayout.ld
View file

@ -44,8 +44,8 @@ SECTIONS
DRAM_START(0x40000000)
DRAM_DMA(0x40000000, 1M)
POSTRAM_CBFS_CACHE(0x40100000, 2M)
RAMSTAGE(0x40300000, 2M)
POSTRAM_CBFS_CACHE(0x40100000, 8M)
RAMSTAGE(0x40900000, 2M)
BL31(0x54600000, 0x60000)
}

4
src/soc/mediatek/mt8192/include/soc/memlayout.ld
View file

@ -53,8 +53,8 @@ SECTIONS
DRAM_START(0x40000000)
DRAM_DMA(0x40000000, 1M)
POSTRAM_CBFS_CACHE(0x40100000, 2M)
RAMSTAGE(0x40300000, 2M)
POSTRAM_CBFS_CACHE(0x40100000, 8M)
RAMSTAGE(0x40900000, 2M)
BL31(0x54600000, 0x60000)
}

4
src/soc/mediatek/mt8195/include/soc/memlayout.ld
View file

@ -44,8 +44,8 @@ SECTIONS
DRAM_START(0x40000000)
DRAM_DMA(0x40000000, 1M)
POSTRAM_CBFS_CACHE(0x40100000, 2M)
RAMSTAGE(0x40300000, 2M)
POSTRAM_CBFS_CACHE(0x40100000, 8M)
RAMSTAGE(0x40900000, 2M)
BL31(0x54600000, 0x60000)
}