Kilian Krause bf0ee592f5 soc/intel/alderlake: Make SATA speed limit configurable ... Add support for limiting SATA interface speed through the FSP parameter 'SataSpeedLimit'. This is useful for mainboards with physical design constraints that require operating at lower speeds than what the controller and drives support. The implementation adds a new chip config option that mainboards can set in their devicetree to control this behavior. Change-Id: Ib0a058d006b752975c57851f2418a4e94b3bfcca Signed-off-by: Kilian Krause <kilian.krause@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88951 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2025-08-28 20:09:02 +00:00
..
amd	device/dram: Rename 'USE_DDRx' config options	2025-07-25 17:03:02 +00:00
cavium	soc/cavium: Fix non matching types	2024-08-30 07:34:47 +00:00
example/min86	soc: Add SPDX license headers to Kconfig files	2024-02-18 02:03:37 +00:00
ibm/power9	3rdparty/open-power-signing-utils: add SecureBoot utility for OpenPOWER	2024-09-06 13:55:50 +00:00
intel	soc/intel/alderlake: Make SATA speed limit configurable	2025-08-28 20:09:02 +00:00
mediatek	soc/mediatek: Increase CBFS cache to 8MB in memlayout.ld	2025-08-24 21:18:52 +00:00
nvidia	arch/arm: Add a few ARM targets as supported by CLANG	2024-08-23 10:40:01 +00:00
qualcomm	soc/qualcomm/x1p42100: Use SPMI driver	2025-08-26 02:41:32 +00:00
rockchip	arch/arm: Add a few ARM targets as supported by CLANG	2024-08-23 10:40:01 +00:00
samsung	samsung/exynos5250: Replace 'unsigned long int' by 'unsigned long'	2025-01-15 08:32:16 +00:00
sifive	tree: Remove unused <assert.h>	2024-11-19 00:40:04 +00:00
ti	soc/ti/am335x: Remove superfluous formats	2024-08-02 14:45:13 +00:00
ucb/riscv	soc/riscv/ucb: Switch to FDT parsing to get memory size	2025-02-26 17:11:09 +00:00
xilinx	soc/xilinx/zynq7000: Initial Xilinx Zynq 7000 SoC bringup	2025-01-23 00:41:01 +00:00