Kilian Krause bf0ee592f5 soc/intel/alderlake: Make SATA speed limit configurable ... Add support for limiting SATA interface speed through the FSP parameter 'SataSpeedLimit'. This is useful for mainboards with physical design constraints that require operating at lower speeds than what the controller and drives support. The implementation adds a new chip config option that mainboards can set in their devicetree to control this behavior. Change-Id: Ib0a058d006b752975c57851f2418a4e94b3bfcca Signed-off-by: Kilian Krause <kilian.krause@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88951 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2025-08-28 20:09:02 +00:00
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amd	device/dram: Rename 'USE_DDRx' config options	2025-07-25 17:03:02 +00:00
cavium
example/min86
ibm/power9
intel	soc/intel/alderlake: Make SATA speed limit configurable	2025-08-28 20:09:02 +00:00
mediatek	soc/mediatek: Increase CBFS cache to 8MB in memlayout.ld	2025-08-24 21:18:52 +00:00
nvidia
qualcomm	soc/qualcomm/x1p42100: Use SPMI driver	2025-08-26 02:41:32 +00:00
rockchip
samsung	samsung/exynos5250: Replace 'unsigned long int' by 'unsigned long'	2025-01-15 08:32:16 +00:00
sifive
ti
ucb/riscv	soc/riscv/ucb: Switch to FDT parsing to get memory size	2025-02-26 17:11:09 +00:00
xilinx	soc/xilinx/zynq7000: Initial Xilinx Zynq 7000 SoC bringup	2025-01-23 00:41:01 +00:00