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soc/qualcomm/x1p42100: Support to load CPUCP firmware in x1p42100

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CPUCP firmware along with its corresponding DTB must be loaded
and then taken out of reset from coreboot to initialize the CPUCP
subsystem. This patch adds support to load CPUCP and CPUCP DTB
firmware in X1P42100. The register details are part of
HRD-X1P42100-S1 document.
https://docs.qualcomm.com/bundle/resource/topics/HRD-X1P42100-S1/

TEST=1. Create an image.serial.bin and ensure it boots on X1P42100.
2. Verified using CPUCP load log from coreboot.
```
[INFO ]  CBFS: Found 'fallback/cpucp_dtbs' @0xe5580 size 0x163 in mcache
		 @0xff7dd714
[INFO ]  VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not
		supported for secdata_kernel v0, return 0
[INFO ]  VB2:vb2_digest_init() 355 bytes, hash algo 2, HW acceleration
		forbidden
[DEBUG]  Loading segment from ROM address 0x9f8040f8
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x81240000 memsize 0x103c srcaddr
		0x9f804130 filesize 0x12b
[DEBUG]  Loading Segment: addr: 0x81240000 memsz: 0x000000000000103c
		filesz: 0x000000000000012b
[DEBUG]  using LZMA
[SPEW ]  [ 0x81240000, 8124103c, 0x8124103c) <- 9f804130
[DEBUG]  Loading segment from ROM address 0x9f804114
[DEBUG]    Entry Point 0x81240000
[SPEW ]  Loaded segments
[DEBUG]  SOC:CPUCP DTBS image loaded successfully.
[INFO ]  CBFS: Found 'fallback/cpucp' @0xbe8c0 size 0x2607d in mcache
		@0xff7dd658
[DEBUG]  read SPI 0xcee914 0x2607d: 12635 us, 12328 KB/s, 98.624 Mbps
[INFO ]  VB2:vb2_secdata_kernel_get() VB2_SECDATA_KERNEL_FLAGS not
		supported for secdata_kernel v0, return 0
[INFO ]  VB2:vb2_digest_init() 155773 bytes, hash algo 2, HW
		acceleration forbidden
[DEBUG]  Loading segment from ROM address 0x9f8040f8
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x1cb00000 memsize 0x2a628 srcaddr
		0x9f8041f4 filesize 0x11c6f
[DEBUG]  Loading Segment: addr: 0x1cb00000 memsz: 0x000000000002a628
		filesz: 0x0000000000011c6f
[DEBUG]  using LZMA
[SPEW ]  [ 0x1cb00000, 1cb21950, 0x1cb2a628) <- 9f8041f4
[DEBUG]  Clearing Segment: addr: 0x000000001cb21950 memsz:
		0x0000000000008cd8
[DEBUG]  Loading segment from ROM address 0x9f804114
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x1cb2b000 memsize 0xb520 srcaddr
		0x9f815e63 filesize 0x134e
[DEBUG]  Loading Segment: addr: 0x1cb2b000 memsz: 0x000000000000b520
		filesz: 0x000000000000134e
[DEBUG]  using LZMA
[SPEW ]  [ 0x1cb2b000, 1cb36520, 0x1cb36520) <- 9f815e63
[DEBUG]  Loading segment from ROM address 0x9f804130
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x1cb3e000 memsize 0x890 srcaddr
		0x9f8171b1 filesize 0x23
[DEBUG]  Loading Segment: addr: 0x1cb3e000 memsz: 0x0000000000000890
		filesz: 0x0000000000000023
[DEBUG]  using LZMA
[SPEW ]  [ 0x1cb3e000, 1cb3e890, 0x1cb3e890) <- 9f8171b1
[DEBUG]  Loading segment from ROM address 0x9f80414c
[DEBUG]    BSS 0x1cb3f000 (4096 byte)
[DEBUG]  Loading Segment: addr: 0x1cb3f000 memsz: 0x0000000000001000
		filesz: 0x0000000000000000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0x1cb3f000, 1cb3f000, 0x1cb40000) <- 9f8171d4
[DEBUG]  Clearing Segment: addr: 0x000000001cb3f000 memsz:
		0x0000000000001000
[DEBUG]  Loading segment from ROM address 0x9f804168
[DEBUG]    BSS 0x81200000 (38916 byte)
[DEBUG]  Loading Segment: addr: 0x81200000 memsz: 0x0000000000009804
		filesz: 0x0000000000000000
[DEBUG]  it's not compressed!
[SPEW ]  [ 0x81200000, 81200000, 0x81209804) <- 9f8171d4
[DEBUG]  Clearing Segment: addr: 0x0000000081200000 memsz:
		0x0000000000009804
[DEBUG]  Loading segment from ROM address 0x9f804184
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x81250000 memsize 0x11068 srcaddr
		0x9f8171d4 filesize 0xe59
[DEBUG]  Loading Segment: addr: 0x81250000 memsz: 0x0000000000011068
		filesz: 0x0000000000000e59
[DEBUG]  using LZMA
[SPEW ]  [ 0x81250000, 81261068, 0x81261068) <- 9f8171d4
[DEBUG]  Loading segment from ROM address 0x9f8041a0
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x81280000 memsize 0xc628 srcaddr
		0x9f81802d filesize 0x6d09
[DEBUG]  Loading Segment: addr: 0x81280000 memsz: 0x000000000000c628
		filesz: 0x0000000000006d09
[DEBUG]  using LZMA
[SPEW ]  [ 0x81280000, 8128c628, 0x8128c628) <- 9f81802d
[DEBUG]  Loading segment from ROM address 0x9f8041bc
[DEBUG]    data (compression=1)
[DEBUG]    New segment dstaddr 0x81290000 memsize 0x31bf8 srcaddr
		0x9f81ed36 filesize 0xb43f
[DEBUG]  Loading Segment: addr: 0x81290000 memsz: 0x0000000000031bf8
		filesz: 0x000000000000b43f
[DEBUG]  using LZMA
[SPEW ]  [ 0x81290000, 812c1bf8, 0x812c1bf8) <- 9f81ed36
[DEBUG]  Loading segment from ROM address 0x9f8041d8
[DEBUG]    Entry Point 0x1cb00000
[SPEW ]  Loaded segments
[DEBUG]  SOC:CPUCP image loaded successfully.
[DEBUG]  CPU_CLUSTER: 0 init finished in 735 msecs
```

Change-Id: I195f038b2380de7796691f0194cf3e39f8d9a991
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88815
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Swathi Tamilselvan 2025-08-18 12:48:25 +05:30 • committed by Subrata Banik
commit cec34128d0
4 changed files with 37 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

7
src/soc/qualcomm/x1p42100/Makefile.mk
View file

@ -210,6 +210,13 @@ $(CPUCP_META_CBFS)-type := raw
$(CPUCP_META_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
cbfs-files-y += $(CPUCP_META_CBFS)
################################################################################
CPUCP_DTBS_FILE := $(X1P42100_BLOB)/cpucp/cpucp_dtbs.elf
CPUCP_DTBS_CBFS := $(CONFIG_CBFS_PREFIX)/cpucp_dtbs
$(CPUCP_DTBS_CBFS)-file := $(CPUCP_DTBS_FILE)
$(CPUCP_DTBS_CBFS)-type := payload
$(CPUCP_DTBS_CBFS)-compression := $(CBFS_COMPRESS_FLAG)
cbfs-files-y += $(CPUCP_DTBS_CBFS)
################################################################################
SHRM_FILE := $(X1P42100_BLOB)/shrm/shrm.elf

28
src/soc/qualcomm/x1p42100/cpucp_load_reset.c
View file

@ -1,13 +1,29 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <console/console.h>
#include <program_loading.h>
#include <soc/cpucp.h>
void cpucp_prepare(void)
{
/* Placeholder */
}
#include <device/mmio.h>
#include <soc/addressmap.h>
void cpucp_fw_load_reset(void)
{
/* Placeholder */
struct prog cpucp_dtbs_prog =
PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp_dtbs");
if (!selfload(&cpucp_dtbs_prog))
die("SOC image: CPUCP DTBS load failed");
printk(BIOS_DEBUG, "SOC image: CPUCP DTBS image loaded successfully.\n");
struct prog cpucp_fw_prog =
PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp");
if (!selfload(&cpucp_fw_prog))
die("SOC image: CPUCP load failed");
printk(BIOS_DEBUG, "SOC image: CPUCP image loaded successfully.\n");
write32((void *) HWIO_APSS_CPUCP_CPUCP_LPM_SEQ_WAIT_EVT_CTRL_MASK_ADDR, 0x0);
setbits32((void *) HWIO_APSS_CPUCP_CPUCP_SW_WAKEUP_REQ_ADDR, 0x1);
}

6
src/soc/qualcomm/x1p42100/include/soc/addressmap.h
View file

@ -15,6 +15,12 @@
#define NCC0_NCC_CMU_NCC_PLL_CFG 0x199A2010
#define NCC0_NCC_CMU_NCC_CLK_CFG 0x199A2030
/* CPUCP */
#define APSS_HM_BASE 0x17000000
#define APSS_CPUCP_LPM_BFSM_REG_BASE (APSS_HM_BASE + 0x019d0000)
#define HWIO_APSS_CPUCP_CPUCP_LPM_SEQ_WAIT_EVT_CTRL_MASK_ADDR (APSS_CPUCP_LPM_BFSM_REG_BASE + 0x161c)
#define HWIO_APSS_CPUCP_CPUCP_SW_WAKEUP_REQ_ADDR (APSS_CPUCP_LPM_BFSM_REG_BASE + 0x1688)
/* X1P42100 QSPI GPIO PINS */
#define QSPI_CS GPIO(132)
#define QSPI_DATA_0 GPIO(128)

3
src/soc/qualcomm/x1p42100/soc.c
View file

@ -5,6 +5,7 @@
#include <soc/mmu_common.h>
#include <soc/symbols_common.h>
#include <soc/pcie.h>
#include <soc/cpucp.h>
static struct device_operations pci_domain_ops = {
.read_resources = &qcom_pci_domain_read_resources,
@ -37,7 +38,7 @@ static void soc_read_resources(struct device *dev)
static void soc_init(struct device *dev)
{
/* placeholder */
cpucp_fw_load_reset();
}
static struct device_operations soc_ops = {