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soc/qualcomm/cmn/qclib: Support reuse of existing DDR training data

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This patch adds support to skip DDR training when valid training data
is available in flash.

The exact size of the training data is passed to ensure accurate hash
computation. A hash is computed on the DDR training data using the
specified size and compared with the stored hash in the header. This
requires passing only the exact training data size to ensure correct
validation.

TEST=Create an image.serial.bin and ensure it boots on X1P42100. Verify
that the DDR training is skipped when valid data is available in flash.

w/o this patch: doing RW_MRC_CACHE update in every boot.

```
[DEBUG]  MRC: Checking cached data update for 'RW_MRC_CACHE'.
[DEBUG]  read SPI 0xc1f290 0xf27c: 5010 us, 12390 KB/s, 99.120 Mbps
[DEBUG]  MRC: cache data 'RW_MRC_CACHE' needs update.
[DEBUG]  MRC: updated 'RW_MRC_CACHE'.
```

w/ this patch: no need to perform RW_MRC_CACHE update.

```
[DEBUG]  FMAP: area RW_MRC_CACHE found @ c10000 (65536 bytes)
[DEBUG]  read SPI 0xc10024 0xf268: 5016 us, 12371 KB/s, 98.968 Mbps
```

Change-Id: I1a5ad0766ea77b22e6a8cb97c24a90c24629dfd0
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88742
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit is contained in:
Swathi Tamilselvan 2025-08-10 23:03:20 -07:00 • committed by Subrata Banik
commit e31fbc493d
1 changed files with 2 additions and 1 deletions
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3
src/soc/qualcomm/common/qclib.c
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@ -252,9 +252,10 @@ void qclib_load_and_run(void)
if (data_size < 0) {
printk(BIOS_ERR, "Unable to load previous training data.\n");
memset(_ddr_training, 0, REGION_SIZE(ddr_training));
data_size = REGION_SIZE(ddr_training);
}
qclib_add_if_table_entry(QCLIB_TE_DDR_TRAINING_DATA,
_ddr_training, REGION_SIZE(ddr_training), 0);
_ddr_training, data_size, 0);
/* Address and size of this entry will be filled in by QcLib. */
qclib_add_if_table_entry(QCLIB_TE_MEM_CHIP_INFO, NULL, 0, 0);