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soc/amd/common/block/psp/psp_smi_flash: Fix busy check

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The busy check is only supported on Fam 17h Picasso and Raven Ridge.
On other platforms the register might not exist and the bits always
read as ones. This prevents the PSP SMI handler from accessing
the SPI flash.

TEST: Ensured that the code does not block on 1Ah platforms.

Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com>
Change-Id: I063b7cd66a5058ae558ad36e4a7dd89a48f718a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
This commit is contained in:
Patrick Rudolph 2025-07-08 08:25:27 +02:00 • committed by Matt DeVillier
commit c13eadeadb
1 changed files with 8 additions and 3 deletions
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11
src/soc/amd/common/block/psp/psp_smi_flash.c
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@ -94,10 +94,15 @@ static enum mbox_p2c_status find_psp_spi_flash_device_region(uint64_t target_nv_
static bool spi_controller_busy(void)
{
const bool busy = (spi_read8(SPI_MISC_CNTRL) & SPI_SEMAPHORE_DRIVER_LOCKED);
bool busy = false;
if (busy)
printk(BIOS_NOTICE, "PSP: SPI controller busy\n");
if (CONFIG(SOC_AMD_PICASSO)) {
// Only implemented on Picasso and Raven Ridge
busy = (spi_read8(SPI_MISC_CNTRL) & SPI_SEMAPHORE_DRIVER_LOCKED);
if (busy)
printk(BIOS_NOTICE, "PSP: SPI controller busy\n");
}
return busy;
}