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soc/mediatek/common/dp: Move mtk_edp_init to dptx_common.c

Browse source 
mtk_edp_init is similar in dptx_v1.c and dptx_v2.c. Make mtk_edp_init
common by

1. Extract dptx_set_tx_power_con and dptx_set_26mhz_clock to
   edp_power_on.
2. Add dptx_hal_phy_init weak function for the platform which does not
   require initialization.

TEST=emerge-cherry coreboot && emerge-rauru coreboot

Change-Id: I686208c6bf8538354fb4fd238755899b0ef8f86b
Signed-off-by: Yidi Lin <yidilin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Yidi Lin 2025-07-28 11:48:44 +08:00
commit 6bb1ba95e1
7 changed files with 67 additions and 102 deletions
Download patch file Download diff file Expand all files Collapse all files

61
src/soc/mediatek/common/dp/dptx_common.c
View file

@ -70,7 +70,7 @@ bool dptx_auxread_dpcd(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr,
return ret;
}
int dptx_get_edid(struct mtk_dp *mtk_dp, struct edid *out)
static int dptx_get_edid(struct mtk_dp *mtk_dp, struct edid *out)
{
int ret;
u8 edid[EDID_BUF_SIZE];
@ -401,7 +401,7 @@ static void dptx_set_dptxout(struct mtk_dp *mtk_dp)
dptx_set_tu(mtk_dp);
}
void dptx_check_sinkcap(struct mtk_dp *mtk_dp)
static void dptx_check_sinkcap(struct mtk_dp *mtk_dp)
{
u8 buffer[16];
@ -511,3 +511,60 @@ void dptx_video_config(struct mtk_dp *mtk_dp)
dptx_set_color_depth(mtk_dp, mtk_dp->info.depth);
dptx_set_color_format(mtk_dp, mtk_dp->info.format);
}
static void dptx_init_port(struct mtk_dp *mtk_dp)
{
dptx_hal_phy_setidlepattern(mtk_dp, true);
dptx_hal_init_setting(mtk_dp);
dptx_hal_aux_setting(mtk_dp);
dptx_hal_digital_setting(mtk_dp);
dptx_hal_phy_init(mtk_dp);
dptx_hal_phy_setting(mtk_dp);
dptx_hal_hpd_detect_setting(mtk_dp);
dptx_hal_digital_swreset(mtk_dp);
dptx_hal_analog_power_en(mtk_dp, true);
dptx_hal_hpd_int_en(mtk_dp, true);
}
__weak void dptx_power_on(void) { /* do nothing */ };
int mtk_edp_init(struct mtk_dp *mtk_dp, struct edid *edid)
{
dptx_power_on();
dptx_init_variable(mtk_dp);
dptx_init_port(mtk_dp);
if (!dptx_hal_hpd_high(mtk_dp)) {
printk(BIOS_ERR, "HPD is low\n");
return -1;
}
dptx_check_sinkcap(mtk_dp);
if (dptx_get_edid(mtk_dp, edid) != 0) {
printk(BIOS_ERR, "Failed to get EDID\n");
return -1;
}
if (dptx_set_trainingstart(mtk_dp) != DPTX_PASS) {
printk(BIOS_ERR, "%s: Failed to set training start\n", __func__);
return -1;
}
dp_intf_config(edid);
dptx_video_config(mtk_dp);
return 0;
}
int mtk_edp_enable(struct mtk_dp *mtk_dp)
{
if (!mtk_dp) {
printk(BIOS_ERR, "%s: eDP is not initialized\n", __func__);
return -1;
}
dptx_video_enable(mtk_dp, true);
return 0;
}

2
src/soc/mediatek/common/dp/dptx_hal_common.c
View file

@ -563,3 +563,5 @@ void dptx_hal_analog_power_en(struct mtk_dp *mtk_dp, bool enable)
DP_WRITE2BYTE(mtk_dp, 0x0038, 0x555);
}
}
__weak void dptx_hal_phy_init(struct mtk_dp *mtk_dp) { /* do nothing */ }

46
src/soc/mediatek/common/dp/dptx_v1.c
View file

@ -357,7 +357,7 @@ static void dptx_training_changemode(struct mtk_dp *mtk_dp)
mdelay(2);
}
static int dptx_set_trainingstart(struct mtk_dp *mtk_dp)
int dptx_set_trainingstart(struct mtk_dp *mtk_dp)
{
u8 lanecount;
u8 linkrate;
@ -453,47 +453,3 @@ static int dptx_set_trainingstart(struct mtk_dp *mtk_dp)
return DPTX_TRANING_FAIL;
}
static void dptx_init_port(struct mtk_dp *mtk_dp)
{
dptx_hal_phy_setidlepattern(mtk_dp, true);
dptx_hal_init_setting(mtk_dp);
dptx_hal_aux_setting(mtk_dp);
dptx_hal_digital_setting(mtk_dp);
dptx_hal_phy_setting(mtk_dp);
dptx_hal_hpd_detect_setting(mtk_dp);
dptx_hal_digital_swreset(mtk_dp);
dptx_hal_analog_power_en(mtk_dp, true);
dptx_hal_hpd_int_en(mtk_dp, true);
}
int mtk_edp_init(struct mtk_dp *mtk_dp, struct edid *edid)
{
dptx_init_variable(mtk_dp);
dptx_init_port(mtk_dp);
if (!dptx_hal_hpd_high(mtk_dp)) {
printk(BIOS_ERR, "HPD is low\n");
return -1;
}
dptx_check_sinkcap(mtk_dp);
if (dptx_get_edid(mtk_dp, edid) != 0) {
printk(BIOS_ERR, "Failed to get EDID\n");
return -1;
}
dptx_set_trainingstart(mtk_dp);
dp_intf_config(edid);
dptx_video_config(mtk_dp);
return 0;
}
int mtk_edp_enable(struct mtk_dp *mtk_dp)
{
dptx_video_enable(mtk_dp, true);
return 0;
}

54
src/soc/mediatek/common/dp/dptx_v2.c
View file

@ -247,7 +247,7 @@ static int mtk_edp_train_eq(struct mtk_dp *mtk_dp, u8 lane_count)
return DPTX_TIMEOUT;
}
static int dptx_set_trainingstart(struct mtk_dp *mtk_dp)
int dptx_set_trainingstart(struct mtk_dp *mtk_dp)
{
u8 lanecount;
u8 linkrate;
@ -354,59 +354,9 @@ static int dptx_set_trainingstart(struct mtk_dp *mtk_dp)
return DPTX_PASS;
}
static void dptx_init_port(struct mtk_dp *mtk_dp)
{
dptx_hal_phy_setidlepattern(mtk_dp, true);
dptx_hal_init_setting(mtk_dp);
dptx_hal_aux_setting(mtk_dp);
dptx_hal_digital_setting(mtk_dp);
dptx_hal_phy_init(mtk_dp);
dptx_hal_phy_setting(mtk_dp);
dptx_hal_hpd_detect_setting(mtk_dp);
dptx_hal_digital_swreset(mtk_dp);
dptx_hal_analog_power_en(mtk_dp, true);
dptx_hal_hpd_int_en(mtk_dp, true);
}
int mtk_edp_init(struct mtk_dp *mtk_dp, struct edid *edid)
void dptx_power_on(void)
{
dptx_set_tx_power_con();
dptx_set_26mhz_clock();
udelay(50);
dptx_init_variable(mtk_dp);
dptx_init_port(mtk_dp);
if (!dptx_hal_hpd_high(mtk_dp)) {
printk(BIOS_ERR, "HPD is low\n");
return -1;
}
dptx_check_sinkcap(mtk_dp);
if (dptx_get_edid(mtk_dp, edid) != 0) {
printk(BIOS_ERR, "Failed to get EDID\n");
return -1;
}
if (dptx_set_trainingstart(mtk_dp) != DPTX_PASS) {
printk(BIOS_ERR, "%s: Failed to set training start\n", __func__);
return -1;
}
dp_intf_config(edid);
dptx_video_config(mtk_dp);
return 0;
}
int mtk_edp_enable(struct mtk_dp *mtk_dp)
{
if (!mtk_dp) {
printk(BIOS_ERR, "%s: eDP is not initialized\n", __func__);
return -1;
}
dptx_video_enable(mtk_dp, true);
return 0;
}

4
src/soc/mediatek/common/dp/include/soc/dptx_common.h
View file

@ -223,19 +223,19 @@ int mtk_edp_enable(struct mtk_dp *mtk_dp);
void dptx_set_tx_power_con(void);
void dptx_set_26mhz_clock(void);
int dptx_set_trainingstart(struct mtk_dp *mtk_dp);
bool dptx_auxread_dpcd(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr,
size_t length, u8 *rxbuf);
bool dptx_auxwrite_dpcd(struct mtk_dp *mtk_dp, u8 cmd, u32 dpcd_addr,
size_t length, u8 *data);
bool dptx_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
int lane_count);
void dptx_check_sinkcap(struct mtk_dp *mtk_dp);
bool dptx_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
int lane_count);
void dptx_init_variable(struct mtk_dp *mtk_dp);
int dptx_get_edid(struct mtk_dp *mtk_dp, struct edid *out);
void dptx_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
void dptx_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
void dptx_power_on(void);
void dptx_video_config(struct mtk_dp *mtk_dp);
void dptx_video_enable(struct mtk_dp *mtk_dp, bool enable);

1
src/soc/mediatek/common/dp/include/soc/dptx_hal_common.h
View file

@ -102,5 +102,6 @@ void dptx_hal_set_color_depth(struct mtk_dp *mtk_dp, u8 color_depth);
void dptx_hal_set_color_format(struct mtk_dp *mtk_dp, u8 color_format);
void dptx_hal_set_txrate(struct mtk_dp *mtk_dp, u8 value);
void dptx_hal_analog_power_en(struct mtk_dp *mtk_dp, bool enable);
void dptx_hal_phy_init(struct mtk_dp *mtk_dp);
#endif /* SOC_MEDIATEK_COMMON_DP_DPTX_HAL_COMMON_H */

1
src/soc/mediatek/common/dp/include/soc/dptx_hal_v2.h
View file

@ -20,7 +20,6 @@ extern const int dptx_hal_driving_offset[];
extern const int dptx_hal_driving_offset_size;
void dptx_hal_swing_emp_reset(struct mtk_dp *mtk_dp);
void dptx_hal_phy_init(struct mtk_dp *mtk_dp);
void dptx_hal_phy_set_idle_pattern(struct mtk_dp *mtk_dp, u8 lane_count, bool enable);
void dptx_hal_phy_set_lanes(struct mtk_dp *mtk_dp, u8 lane_count);