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soc/qualcomm/x1p42100: Reserve DDR memory regions for AOP and BL31

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Updated the memory layout file to include necessary DDR region
reservations for AOP and BL31.

TEST=Create an image.serial.bin and ensure it boots on X1P42100.

Change-Id: I67b0210dfc563c0a0e8f879b1f41693e1d0e6384
Signed-off-by: Swathi Tamilselvan <tswathi@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Swathi Tamilselvan 2025-08-08 13:58:48 +05:30 • committed by Subrata Banik
commit 90589d44d2
2 changed files with 6 additions and 2 deletions
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3
src/soc/qualcomm/x1p42100/memlayout.ld
View file

@ -57,7 +57,8 @@ SECTIONS
REGION(shrm, 0x24040000, 128K , 4K)
DRAM_START(0x80000000)
REGION(dram_aop, 0x81c00000, 0x0a0000, 0x1000)
POSTRAM_CBFS_CACHE(0x9F800000, 16M)
RAMSTAGE(0xA0800000, 16M)
BL31(0xC0000000, 1M)
BL31(0xD80D6000, 1M)
}

5
src/soc/qualcomm/x1p42100/soc.c
View file

@ -1,6 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/device.h>
#include <soc/mmu.h>
#include <soc/mmu_common.h>
#include <soc/symbols_common.h>
#include <soc/pcie.h>
@ -12,7 +14,8 @@ static struct device_operations pci_domain_ops = {
};
static void soc_read_resources(struct device *dev)
{
/* placeholder */
ram_range(dev, 0, (uintptr_t)region_offset(ddr_region), region_sz(ddr_region));
reserved_ram_range(dev, 1, (uintptr_t)_dram_aop, REGION_SIZE(dram_aop));
}
static void soc_init(struct device *dev)