soc/mediatek/common: Increase per-channel SPMI max byte count to 2
In the scenario of suspend, when the SPM firmware attempts to turn off the VDDQ and VMDDR power supplies, the command sent is rejected by PMIF, resulting in a system hang. The reason is that SPM simultaneously wrote two registers (two bytes), while the original configuration only allowed reading or writing one byte at a time. Modify the maximum number of bytes that an SPMI user can read or write in a single operation to meet the requirement of reading or writing 16 bits at once. BUG=b:420874944 BRANCH=skywalker TEST=2-byte R/W passed; suspend-resume verified successfully. Change-Id: I46ace45564328c46ab340b74d73e3574957e36ef Signed-off-by: Niklaus Liu <niklaus.liu@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88790 Reviewed-by: Vince Liu <vince-wl.liu@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Niklaus Liu <niklaus.liu@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
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1 changed files with 9 additions and 7 deletions
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@ -104,14 +104,16 @@ static void pmif_spmi_enable(struct pmif *arb)
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pmif_spmi_config(arb);
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/*
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* set bytecnt max limitation.
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* hw bytecnt indicate when we set 0, it can send 1 byte;
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* set 1, it can send 2 byte.
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* Set max bytecnt. For each 32-bit reg, 4 bits indicate one channel.
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* 0x0 means max bytecnt = 1.
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* 0x1 means max bytecnt = 2.
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* Here we set max bytecnt to 2 for all channels.
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*/
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write32(&arb->mtk_pmif->inf_max_bytecnt_per_0, 0);
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write32(&arb->mtk_pmif->inf_max_bytecnt_per_1, 0);
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write32(&arb->mtk_pmif->inf_max_bytecnt_per_2, 0);
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write32(&arb->mtk_pmif->inf_max_bytecnt_per_3, 0);
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write32(&arb->mtk_pmif->inf_max_bytecnt_per_0, 0x11111111);
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write32(&arb->mtk_pmif->inf_max_bytecnt_per_1, 0x11111111);
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write32(&arb->mtk_pmif->inf_max_bytecnt_per_2, 0x11111111);
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write32(&arb->mtk_pmif->inf_max_bytecnt_per_3, 0x11111111);
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/* Add latency limitation */
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write32(&arb->mtk_pmif->lat_cnter_en, PMIF_SPMI_INF);
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