Patrick Rudolph c13eadeadb soc/amd/common/block/psp/psp_smi_flash: Fix busy check ... The busy check is only supported on Fam 17h Picasso and Raven Ridge. On other platforms the register might not exist and the bits always read as ones. This prevents the PSP SMI handler from accessing the SPI flash. TEST: Ensured that the code does not block on 1Ah platforms. Signed-off-by: Patrick Rudolph <patrick.rudolph@amd.com> Change-Id: I063b7cd66a5058ae558ad36e4a7dd89a48f718a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/88356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Alicja Michalska <ahplka19@gmail.com>		2025-08-28 20:10:39 +00:00
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amd	soc/amd/common/block/psp/psp_smi_flash: Fix busy check	2025-08-28 20:10:39 +00:00
cavium
example/min86
ibm/power9
intel	soc/intel/alderlake: Make SATA speed limit configurable	2025-08-28 20:09:02 +00:00
mediatek	soc/mediatek: Increase CBFS cache to 8MB in memlayout.ld	2025-08-24 21:18:52 +00:00
nvidia
qualcomm	soc/qualcomm/x1p42100: Use SPMI driver	2025-08-26 02:41:32 +00:00
rockchip
samsung	samsung/exynos5250: Replace 'unsigned long int' by 'unsigned long'	2025-01-15 08:32:16 +00:00
sifive	tree: Remove unused <assert.h>	2024-11-19 00:40:04 +00:00
ti
ucb/riscv	soc/riscv/ucb: Switch to FDT parsing to get memory size	2025-02-26 17:11:09 +00:00
xilinx	soc/xilinx/zynq7000: Initial Xilinx Zynq 7000 SoC bringup	2025-01-23 00:41:01 +00:00