Renames fill_fsps_acoustic_params to fill_fspm_acoustic_params to align
with the naming conventions used for other FSP-M configuration
functions.
Change-Id: I0044c21a8f82dfa2308fade78adbd8bcf844cb63
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit introduces a debug message to the DDR5 memory type
initialization process within the Panther Lake SoC. By adding this log,
developers can gain better insights when diagnosing issues related to
DDR5 memory configurations.
BUG=none
TEST=Verify the debug message is displayed during DDR5 initialization.
Change-Id: I77ceea0f7a29983dd2e4ad1af26a0383721d7ca0
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89331
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit removes the unused `lp_ddr_dq_dqs_re_training` field from
various memory configuration structures across multiple mainboard
variants, including google/fatcat, google/ocelot, and intel/ptlrvp.
This change should reduce complexity and prevent unnecessary memory
operations related to DQ/DQS retraining.
Write DqDqs retraining is enabled in Intel FSP by default. This can be
verified with debug FSP logs by checking WRTRETRAIN and
"MRC task -- Write DQ/DQS Retraining -- Started." prints.
BUG=None
TEST=Boot to OS on google fatcat board and verify DQ/DQS retraining.
Change-Id: Ib298b06260f576bee1f078dc09b1e23a9772b431
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89334
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit f3211e9639 ("soc/intel/pantherlake: Add support for Acoustic
Noise Mitigation UPDs") introduced minor coding convention
violations. These are being addressed as follows:
- Renames fill_fsps_acoustic_params to fill_fspm_acoustic_params to
align with the naming conventions used for other FSP-M configuration
functions.
- Removes an unnecessary empty line.
- Aligns function parameters.
Change-Id: I8652c2fee71c8e2742146b5e622633de78c1c17e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89332
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
In order to build for PantherLake with TME disabled, key generation
needs to depend on TME Kconfig.
Change-Id: I0af438e279f422292302387442489bcbc1b1605f
Signed-off-by: Alicja Michalska <alicja.michalska@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89226
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit addresses a potential low power state over-consumption
issue. This issue could arise if SPI DMA has been locked down while a
transfer was still marked as active, typically if a SPI DMA transfer
failed and hung.
The fast_spi_dma_lock() function now checks if a DMA transfer is ongoing
and ensures that it is marked as complete before locking the DMA control
register.
Change-Id: I5e08991b2160a43013b129d302c46fc229f2286d
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88913
Reviewed-by: Zhixing Ma <zhixing.ma@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
This commit adds support for a new Panther Lake B0 SKU CPUID c06c3.
BUG=b:444497427
TEST=Successfully boot a fatcat device with new Panther Lake B0.
coreboot displays the following log:
CPU: ID c06c3, Pantherlake B0, ucode: 0000010c
Change-Id: Id2c1caf8d6845bb16a94314c4e9a214def06efee
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89150
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
SlowSlewRate, AcousticNoiseMitigation and FastPkgCRampDisable upds
can be overwritten with this patch.
BUG=none
TEST=Able to override the acoustic noise UPDs.
Change-Id: I5bfa98834f8d7cfcaab3fdbb7dde914d78529581
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Add mapping of different SKUs based on CPU ID and TDP values.
Add PowerLimits (PL) values.
Add i_trip value for Fast Vmode.
Note: The i_trip value, the value at which the Voltage Regulator (VR)
or SoC will trigger a protective action such as throttling or
entering Fast Vmode is, due to not being documented, currently set at
70% of the maximum current the VR is designed to support for a rail.
The actual i_trip value to be updated once it is available.
Ref=858124 Power Delivery Guide Rev1p0
830097 Powermap Rev1p1
BUG=b:433211504
TEST= Build Ocelot and verify it compiles without any error.
check CPU log for the following error
[ERROR] Could not find the SKU power map
With the current patch this error line is not seen in the CPU log
anymore.
Change-Id: I8c54efc8eb360ed6f814a336448bb204d5ab0268
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88858
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit introduces a new configuration structure for the
Connectivity Integration (CNVi) block in Intel SoCs.
The added soc_intel_common_block_cnvi_config structure, located in
chip.h, defines a wake pin that specifies the ACPI Power Resources for
Wake (_PRW), enabling wake-up capabilities from sleep states.
This enhancement provides a structured way to handle CNVi
configurations, which is crucial for managing device power states and
ensuring proper wake functionalities as defined by ACPI standards.
Change-Id: Ide6dea04cb089d73fe6aad9fb91044f9eb43edc6
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
This commit adds support for logging Bluetooth device wake events in the
Pantherlake platform. It improves visibility into wake events triggered
by Bluetooth devices, which is crucial for debugging and power
management analysis.
Change-Id: I36bb08075e79ab3151cfdaf41ace2121aaac0973
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89057
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit updates the PCIe root port numbering for Wildcat Lake
as per the revised EDS document. This update ensures alignment with
the PCIe root port architecture.
Current:
- Bus-Device-Function: 0h – 6h – 0h = Root Port 5
- Bus-Device-Function: 0h – 6h – 1h = Root Port 6
New:
- Bus-Device-Function: 0h – 6h – 0h = Root Port 9
- Bus-Device-Function: 0h – 6h – 1h = Root Port 10
This resolves the warning shown during PCIe enumeration in boot
logs.
References:
- Wildcat Lake Platform Message of the Week (#844458)
- Wildcat Lake Processor EDS Volume 1 (#842271)
- Wildcat Lake External Design Specification (EDS) Volume 2 (#829345)
BUG=b:433687705
TEST=Boot the system with the updated firmware and verify that
below warning is not reported for the PCIe root ports:
"[WARN ] pcie_rp_original_idx: Unexpected root-port number '9' at
PCI: 00:06.0, ignoring."
Change-Id: Icf5e3ae3d008f8d79480959bef7b4768fb34b4a8
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Add scan_bus operation to fast_spi device operations to enable
discovery of statically defined child devices.
This allows device drivers such as drivers/pc80/tpm that are
physically connected to the fast_spi bus to be properly
enumerated and initialized during device tree scanning.
Without this change, child devices defined in devicetree under
fast_spi would not be discovered, preventing proper driver
binding and initialization.
Example devicetree configuration:
```
device ref fast_spi on
chip drivers/pc80/tpm # SPI TPM header
device pnp 0c31.0 on end
end
end
```
Without a .scan_bus hook in fast_spi_dev_ops, coreboot's
BS_DEV_ENUMERATE phase never creates the pnp 0c31.0 device. As a
result, in BS_DEV_RESOURCES you see, that the device PNP 0c31.0
is missing its function "read_resources":
```
(in BS_DEV_ENUMERATE)
[DEBUG] scan_bus: bus PCI: 00:00:1f.4 finished in 11 msecs
[DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 1510 msecs
[SPEW ] scan_static_bus for Root Device done
... (in BS_DEV_RESOURCES)
[SPEW ] PCI: 00:00:1f.5 read_resources segment group 0 bus 0
[ERROR] PNP: 0c31.0 missing read_resources
[SPEW ] PCI: 00:00:1f.5 read_resources segment group 0 bus 0 done
[SPEW ] DOMAIN: 00000000 read_resources segment group 0 bus 0 done
[SPEW ] Root Device read_resources segment group 0 bus 0 done
[INFO ] Done reading resources.
```
With the implementation of scan_bus, the log shows that the resources
are allocated correctly:
```
(in BS_DEV_ENUMERATE)
[DEBUG] scan_bus: bus PCI: 00:00:1f.4 finished in 11 msecs
[DEBUG] PCI: 00:00:1f.5 scanning...
[SPEW ] scan_static_bus for PCI: 00:00:1f.5
[DEBUG] PNP: 0c31.0 enabled
[SPEW ] scan_static_bus for PCI: 00:00:1f.5 done
[DEBUG] scan_bus: bus PCI: 00:00:1f.5 finished in 14 msecs
[DEBUG] scan_bus: bus DOMAIN: 00000000 finished in 1536 msecs
[SPEW ] scan_static_bus for Root Device done
... (in BS_DEV_RESOURCES)
[SPEW ] PCI: 00:00:1f.5 read_resources segment group 0 bus 0
[SPEW ] dev: PNP: 0c31.0, index: 0x0, base: 0xfed40000, size: 0x5000
[SPEW ] PCI: 00:00:1f.5 read_resources segment group 0 bus 0 done
[SPEW ] DOMAIN: 00000000 read_resources segment group 0 bus 0 done
[SPEW ] Root Device read_resources segment group 0 bus 0 done
[INFO ] Done reading resources.
```
TEST=Verified on Siemens mc_rpl1 mainboard. TPM device properly
enumerated with scan_bus implementation.
Change-Id: I4049d2d3cd5132362a7efd551dc9dd78cd24b9eb
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88966
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The commit enables memory bandwidth compression for Integrated Graphics
Device (IGD) when IGD is active. This change intends to improve graphics
performance.
BUG=b:431221875
TEST=On a Fatcat device, activating memory bandwidth compression leads
to graphics performance improvements ranging from 20% to 65% on
some graphics workloads.
Change-Id: Ia74fb6bac880a5eb9fe833f071bd129e69345d28
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88910
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
This commit reserves memory resources associated with the memory
bandwidth compression functionality for Intel Integrated Graphics
Devices (IGD). The reservation is achieved by identifying the memory
region in the Resource Hand-Off Blocks (HOB) through a specific GUID,
provided in the FSP integration guide, and then marking it as
reserved. This ensures that the memory compression functionality can
operate without interference from other processes.
BUG=b:441695812
TEST=On a Fatcat device with the MemoryBandwidthCompression UPD set to
1, coreboot logs show both the detection of the HOB and the related
memory resource marked as reserved.
[DEBUG] Memory Compression HOB found: base=0x100000000
length=0x02400000
[...]
[DEBUG] 19. 0000000100000000-00000001023fffff: RESERVED
Change-Id: I21f247dd8aaa88d4ae4da70eb78f7decc1793777
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
This patch increases the hardcoded MTRR region size from 16 MiB to 32
MiB. This ensures a larger portion of memory is cached after the DRAM
phase, which helps in avoiding performance issues in memory-constrained
boots like the pre-DRAM stage. This change is crucial for optimal system
performance.
TEST=Able to boot google/fatcat and save 13ms of the boot time.
w/o this patch:
```
31:device enumeration 1,183,804 (13,341)
```
w/ this patch:
```
31:device enumeration 1,159,612 (359)
```
Change-Id: I25463f1b9e3b82b1a05a8fb7a44df4d188b4731a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88971
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit addresses incorrect Thermal Design Power (TDP) mappings for
Panther Lake-U SKUs. Both 15W and 25W TDPs are now correctly mapped to
the same Power Limit configurations, ensuring consistent handling of
these SKUs.
Below is the collection of documents utilized to address this issue:
1. 815002 Panther Lake H Processor - External Design Specification
Revision. 1.52
2. 813278 Panther Lake H Power Map - Rev 1p6
BUG=None
TEST=Do not see error log "Could not find the SKU power map" and warning
"Skipped power limits configuration for SA PCI ID: 0xb003"
Change-Id: I995183a04b47967dd22ee6f4f3820da7eeb175bf
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88930
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com>
Add support for limiting SATA interface speed through the FSP parameter
'SataSpeedLimit'. This is useful for mainboards with physical design
constraints that require operating at lower speeds than what the
controller and drives support.
The implementation adds a new chip config option that mainboards can
set in their devicetree to control this behavior.
Change-Id: Ib0a058d006b752975c57851f2418a4e94b3bfcca
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88951
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up to the USB ACPI driver and enable the generation of ACPI code
for enabled USB devices.
Change-Id: I53fc73046e4b107064fa8c3c617ba6d9b807b71d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83211
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alicja Michalska <ahplka19@gmail.com>
GNR-AP public FSP
- https://github.com/intel/FSP/tree/master/BirchStreamFspBinPkg/ap
GNR-SP public FSP
- https://github.com/intel/FSP/tree/master/BirchStreamFspBinPkg/sp
GNR mainboards will by default use public FSP bin and headers.
If needing to use site-local FSP bin and headers, apply below
settings in the defconfig (use beechnutcity CRB as example),
CONFIG_FSP_USE_REPO=n
CONFIG_ADD_FSP_BINARIES=y
CONFIG_FSP_T_FILE="site-local/beechnutcity/Server_T.fd"
CONFIG_FSP_M_FILE="site-local/beechnutcity/Server_M.fd"
CONFIG_FSP_S_FILE="site-local/beechnutcity/Server_S.fd"
CONFIG_FSP_HEADER_PATH="src/vendorcode/intel/fsp/fsp2_0/
graniterapids/sp/"
TEST=Build and boot on intel/avenuecity CRB
TEST=Build and boot on intel/beechnutcity CRB
Change-Id: I88701316e21ec4737539294d17926aa0abe8c1fd
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88898
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Hancockc <hancock.chang@mitaccomputing.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Schumi Chu
Reviewed-by: Wilson-MiTACComputing <wilson.chien@mitaccomputing.com>
Reviewed-by: Mark Chang <mark.chang@mitaccomputing.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Granite Rapids SoC has 2 SKUs, a.k.a. GNR-AP and GNR-SP, which
use different FSP headers/binaries. Add Kconfig items to support
these SKU types.
Change-Id: Ie3a2d603f0a2c303e8f3c0911598742fbc25d73a
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88897
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Wilson-MiTACComputing <wilson.chien@mitaccomputing.com>
Reviewed-by: Mark Chang <mark.chang@mitaccomputing.com>
Reviewed-by: Schumi Chu
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rearm and clear functions are called only if a valid crashlog is
present and extracted. If there is no valid crashlog, rearming will
lead to incorrect notification and skipping of the next crashlog event
BUG=b: None
TEST= PMC discovery buffer - rearmed status bit (trig_armed_sts)
MMIO read of Bit position 25 is rearmed status bit
MMIO read of desc_table_addr = (bar_address + offset)
desc_table_addr = 0x9c198000 + 0x1d00 = 0x9c199d00
:1 for cold boot and
:0 for warm boot after manual crash
Change-Id: I42da487abd383567d7945835b738557e2e3fa714
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
After crashlog data is extracted, CPU rearm command is issued to
prepare the crash logging mechanism for future events. Instead of
command and response polling of mailbox, watcher interface which is a
direct MMIO based, low latency control register is used for efficiency.
In PTL, a Crashlog watcher providing control the same way provided by
Crashlog Mailbox Interface used by (mainly) BIOS is used for all CPU
crashlog control requests from BIOS to PUNIT.
BUG=b: None
TEST= Manually trigger crash using command
iotools mmio_write32 (baraddress + watcher offset=0x10) 0x20000000
followed by warm boot, check rearm status - which is 25th bit of
*(bar_address)
Change-Id: I89dd23fad144c1c7122b5536f1ac848ea66ea6b1
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Crashlog storage and power management in PTL is changed to a unified
and persistent model,removing the need for manual SRAM power-down
commands after crashlog extraction.
Change-Id: I5bea1c816bbb68a4b2b21cc3be6cf118b4282fe7
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88512
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Commit 87c9bb3994 ("soc/intel/adl: Fill in SPD data on both channels
of DDR5 memory") accidentally deleted the function
mem_init_override_channel_mask().
Additionally, skip checking for channel 0 while consuming the channel
disable mask.
BUG=none
TEST=CQ
Change-Id: I6217b2801e88b8ab98b2a3acaa0cb9580b05bb64
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88697
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
It doesn't make sense to use CONFIG_DIMM_SPD_SIZE to determine the
amount of data to read from the SPD, then override that value.
Clean up the mess and simply set the SPD length fror the spd_block
struct to CONFIG_DIMM_SPD_SIZE.
Change-Id: Ifec6cf1f6d7c931131460ea72440aa236590d0b6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88523
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 91a1276d53 ("soc/intel/alderlake: Implement WA for DDR5 DIMM
modules") was added to allow FSP to perform the SPD read for DDR5
modules since coreboot did not properly support reading SPD from
EEPROM for DDR5. The same code was copied for Meteorlake.
Now that DDR5 SPD EEPROM reading has been fixed in commit e9cb352706
("soc/common/smbus: Support reading SPD5 hubs for DDR5"), remove the
now unneeded workaround for DDR5 and use coreboot's SPD read as we
do for all other module types.
Change-Id: I600d8fd480cb84d5dcb679e4f0bdeeaaebfab386
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82733
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch applies commit 0e7cf3d81d ("soc/intel/alderlake: Fix DDR5
channel mapping") to Meteor Lake.
DDR5 memory modules have two separate 32-bit channels (40-bit on ECC
memory modules), and the SPD info refers to one channel: the primary
bus width is 32 (or 40) bits and the "DIMM size" is halved. On Meteor
Lake, there are 2 memory controllers with 4 32-bit channels each for
DDR5. FSP has 16 positions to store SPD data, some of which are only
used with LPDDR4/LPDDR5.
To try to make things less confusing, FSP abstracts the DDR5 channels
so that the configuration works like on DDR4. This is done by copying
each DIMM's SPD data to the other half-channel. Thus, fix the wrapper
parameters for DDR5 accordingly.
Change-Id: I00cd1fba855a50422a68fa662df4ca8ed2c6458d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88636
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 91a1276d53 ("soc/intel/alderlake: Implement WA for DDR5 DIMM
modules") was added to allow FSP to perform the SPD read for DDR5
modules since coreboot did not properly support reading SPD from
EEPROM for DDR5.
Now that DDR5 SPD EEPROM reading has been fixed in commit e9cb352706
("soc/common/smbus: Support reading SPD5 hubs for DDR5"), remove the
now unneeded workaround for DDR5 and use coreboot's SPD read as we
do for all other module types.
Change-Id: I5a92199a7cd2718e9396f0dac8257df40e4f834c
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75284
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Introduce the disable_progress_bar setting in configuration to allow
disabling the memory training progress bar during firmware
initialization.
BUG=b:418675387
TEST=After setting disable_progress_bar, memory training progress bar
is disabled.
Change-Id: I35e8191df27c0eda634724580514e980bd620136
Signed-off-by: Alok Agarwal <alok.agarwal@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
DDR5 uses a Serial Presence Detect (SPD) with hub function
(SPD5 hub device) to store the SPD data. The SPD5 hub has 1024 bytes of
EEPROM (`CONFIG_DIMM_SPD_SIZE=1024`).
Ref: DDR5 SDRAM spec, JESD79-5C.01
Change-Id: Ic5e6c58f255bef86b68ce90a4f853bf4e7c7ccfe
Co-authored-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52731
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These will be used in subsequent patches which optimize the reading of
SPDs based on the supported memory type(s).
Change-Id: I8b0d4f37b4b992c42bede25d678cb9afc9db3dd6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88521
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The magic number '1' for VgaInitControl is replaced with the
VGA_INIT_CONTROL_ENABLE macro for improved readability and
maintainability.
This makes the code's intent clearer and aligns with best practices
for using named constants.
The VGA_INIT_CONTROL_ENABLE macro is defined in ux.h along with a
comment to describe its purpose.
TEST=Able to see eSOL while booting google/fatcat.
Change-Id: I27a91030c0aaa52e099869c5870da670d3e28628
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit assigns pci_dev_request_bus_master to the .final operation
for both the DSP and HDA device operations to ensure that the bus
master is enabled.
This change ensures correct PCI configuration for DSP and HDA devices,
preventing potential issues with direct memory access operations.
BUG=b:427091370
TEST=Able to build and boot google/fatcat.
w/o this patch
```
firmware-shell: pcir.b 0 0x1f 3 0x4
0x02
```
w/ this patch:
```
firmware-shell: pcir.b 0 0x1f 3 0x4
0x06
```
Change-Id: Id2480dba08ea8ee7a9219327b8a31f8f9f65410c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
After crash data extraction, the records are cleared and reinitialized
to their default values. This is done using watcher interface instead
of BIOS mailbox commands because of low latency and efficiency.
Ref: LNL FAS 733648
BUG= b:None
TEST= iotools mmio_dump 0x9c199d40 0x10 - PMC
0x000000009c199d40: 0xdeadbeef 0xdeadbeef 0xdeadbeef 0xdeadbeef
iotools mmio_dump 0x9c1d0058 0x10 - CPU
0x000000009c1d0058: 0xcafecafe 0xcafecafe 0xcafecafe 0xcafecafe
Initial 8 bytes of header are zeroes - indicating that both header
and crashlog data buffer are cleared
Change-Id: I8a36e091f61833067caf9e9f94ba79149e699d68
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
FSP-T will help to cache bios region along with MTRR programming
by setting CodeRegionBase/CodeRegionLength, thus there is no need
for xeon_sp platforms to do it.
TEST=Build and boot on intel/avenuecity CRB
TEST=Build and boot on intel/archercity CRB
Check MTRR usage and below duplicated MTRR item get removed:
[DEBUG] 0x00000000ff000005: PHYBASE1: Address = 0x00000000ff000000, WP
[DEBUG] 0x000fffffff000800: PHYMASK1: Length = 0x0000000001000000, Valid
Change-Id: Ia414a35c663f3aa1b02d944475a96e11d07a4f00
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Drop the custom function to retrieve the value of multiple GPIOs
at once as integer value and use the generic function prototype
defined in include/gpio.h instead.
Therefore:
* select GENERIC_GPIO_LIB
* Stub gpio_input(). Existing code assumes the pin is input.
* Drop get_gpios() implementation
* Include new header file gpio.h
* Migrate pins from type int to gpio_t
Migrate all users of the old function to the new function.
Allows to share more code between older x86 Intel boards and newer
x86 Intel boards since they now use a common header.
Change-Id: I2296ff72231b569c618295b36b95a89ffebb3a6e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88503
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to use the common gpio.h header file typedef gpio_t in
soc/gpio.h for Intel common code, Intel lynxpoint and Intel broadwell.
Change-Id: I2049a2cfd75c60d00bdd564b294808760b6aff7f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Rename config options 'USE_DDRx' to 'DRAM_SUPPORT_DDRx' to make them
less clunky, and in preparation to expand their use inside SoC code.
Change-Id: Ie6edd730c5cbad679a90fcf7989a942d9b2dd3d8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <yuchi.chen@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit introduces support for asynchronous coreboot File
System (CBFS) file loading from SPINOR, specifically targeting the
fsps.bin file, in the Intel Panther Lake (PTL) System on a Chip (SoC)
platform. The primary motivation for this change is to improve boot time
performance by utilizing SPI Direct Memory Access (DMA) to preload files
while the Central Processing Unit (CPU) continues executing other tasks.
This feature uses cooperative multithreading. Because the scheduling is
cooperative, the boot process stays mostly predictable, which minimizes
debugging difficulties while still enhancing boot performance.
The preload operations are strategically modified according to the
chipset lockdown settings. This guarantees that payload preloading is
finalized prior to SPI DMA locking when the chipset lockdown is managed
by FSP or otherwise maximizes the pre-loading feature.
Note: As there is no UPD to control the Fast DMI DMA interface lockdown,
a special FSP binary, built without the Fast SPI DMA driver
(PcdSpiDmaEnable), is required when chipset lockdown setting is set to
CHIPSET_LOCKDOWN_COREBOOT.
TEST=On a Fatcat device, with CHIPSET_LOCKDOWN_COREBOOT, the boot time
has improved by around 17-18 ms.
Change-Id: I4106058d382b99eac5f988c134cc02f024f7d473
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88300
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit implements a token-based queuing system to reduce delays
between consecutive DMA operations. The queuing mechanism aims to
improve overall throughput.
A Kconfig option FAST_SPI_DMA_QUEUE_SIZE defines the maximum number of
concurrent DMA transfers that can be queued and processed.
When DMA transfers are queued, a new thread is initiated to run
fast_spi_dma_main_thread(). This function consistently monitors for
available transfer tokens and performs DMA operations when tokens are in
the DMA_REQUESTED state. If there are no tokens in the desired state,
the thread_running flag is set to false, and the thread terminates
smoothly.
While it provides a barely perceptible boot time improvement with the
Panther Lake configuration, it makes the boot flow more consistent and
predictable.
TEST=On a Fatcat device with CBFS_PRELOAD enabled and set up, we observe
consecutive logs as follows, proving a new DMA transfer is issued
as soon as the previous one's completion is detected.
[DEBUG] Fast-SPI: transfer completed in 2574 us
[DEBUG] Fast-SPI: Reading 240 blocks via DMA
Change-Id: Ic5249362041cfa028885874b43893e1d7942ed94
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
In PTL Crashlog Watcher interface is used instead of Mailbox since it
is based on the Intel Platform Monitoring Technology (PMT) standard.
The Watcher interface provides a more flexible and efficient way to
control and monitor crashlog collection. Hence the functionalities like
rearm and clear are implemented using watcher interface instead of BIOS
mailbox to PUNIT.
Change-Id: I24c5c9753a577b255a7129d20ab83f93001a0485
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88500
Reviewed-by: <srinivas.kulkarni@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
After the BIOS reads and processes the crashLog record, it sets the
CONSUMED_BIOS bit to indicate that the reading and storing of crashlog
record is complete. This is read only bit. When this bit is set ,
crashlog discovery and data collection are skipped. This bit helps in
preventing the same crashLog from being extracted multiple times after
a reset.
BUG= b:None
TEST= The header value during warm boot after crash
cpu_cl_disc_tab.header.data dw0=88420003, dw1=0x0
Change-Id: I4b9e6900218f28b6beb71b7667bc1c57f0134a84
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88499
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: <srinivas.kulkarni@intel.com>
This patch refactors the BMP rendering logic, moving it from
drivers/intel/fsp2_0 to src/lib. This centralizes the code
responsible for rendering BMP images to the framebuffer.
Key changes:
- Move BMP rendering functions (e.g., calculate_logo_coordinates,
copy_logo_to_framebuffer) and their dependencies to
src/lib/render_bmp.c and src/lib/render_bmp.h.
- Decouple BMP definitions from UEFI headers by introducing new
coreboot-specific structures for BMP images and BLT pixels.
- Consolidate bootsplash-related declarations into bootsplash.h,
including new `fw_splash_vertical_alignment`,
`fw_splash_horizontal_alignment`, and `struct logo_config`.
- Update `soc_load_logo_by_coreboot` to use the new common
`load_and_render_logo_to_framebuffer` function and `struct
logo_config` for rendering.
- Relocate `release_logo` to `src/lib/render_bmp.c` for better
module structure.
- Update `src/lib/Makefile.mk` to include the new render_bmp.c.
This refactoring improves code organization and reusability, making
BMP rendering accessible without tight coupling to Intel-specific
driver code.
BUG=b:427387842
TEST=Verify firmware splash screen on google/fatcat.
Change-Id: I0e20ea7e44b4b3ccdb2d4aa9b6aa10ed3447ccfc
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88361
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a DMA lock mechanism to secure the Fast SPI DMA operations
during the payload boot phase. A new `fast_spi_dma_lock` function is
added to lock the DMA control register when the system enters the
payload boot state. This ensures that DMA operations are appropriately
secured, preventing any unintended data transfers post-boot.
TEST=On a Fatcat device with an FSP not locking down Fast SPI DMA,
coreboot logs show "Fast-SPI: DMA has been locked." and
/sys/devices/pci0000:00/0000:00:1f.5/config shows that bit 15 of
register FAST_SPI_DMA_CONTROL (0xbc) has been is set.
Change-Id: Ie4abbcfc798480319a32b0049e3559d623ef78ef
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88488
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use microcode updates from intel-microcode submodule by default.
Downstream users can still decide to use their own files.
TEST=Build and boot on intel/avenuecity CRB
TEST=Build and boot on intel/beechnutcity CRB
Change-Id: I5a37423426b19dc9ec76984df5ad9c6d2a28f83b
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
IBL shall use PMC device to program ABASE instead of PCR.
TESTED=Build and boot on intel/avenuecity CRB with below log:
[INFO ] soc_config_acpibase : pmbase = 501
Change-Id: I3497c287a5370deed02b269405bc45d5d41e7f33
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88144
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
