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soc/intel/common/block/systemagent: Increase MTRR region size to 32 MiB

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This patch increases the hardcoded MTRR region size from 16 MiB to 32
MiB. This ensures a larger portion of memory is cached after the DRAM
phase, which helps in avoiding performance issues in memory-constrained
boots like the pre-DRAM stage. This change is crucial for optimal system
performance.

TEST=Able to boot google/fatcat and save 13ms of the boot time.

w/o this patch:

```
    31:device enumeration            1,183,804 (13,341)
```

w/ this patch:

```
    31:device enumeration            1,159,612 (359)
```

Change-Id: I25463f1b9e3b82b1a05a8fb7a44df4d188b4731a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88971
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit is contained in:
Subrata Banik 2025-08-27 23:07:25 +05:30
commit 1c571446ec
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/common/block/systemagent/memmap.c
View file

@ -65,7 +65,7 @@ void fill_postcar_frame(struct postcar_frame *pcf)
/*
* We need to make sure ramstage will be run cached. At this
* point exact location of ramstage in cbmem is not known.
* Instruct postcar to cache 16 megs below cbmem top which is
* Instruct postcar to cache 32 megs below cbmem top which is
* a safe bet to cover ramstage.
*/
printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
@ -77,7 +77,7 @@ void fill_postcar_frame(struct postcar_frame *pcf)
if (ENV_CREATES_CBMEM && CONFIG(SOC_INTEL_COMMON_BASECODE_RAMTOP))
update_ramtop(top_of_ram);
postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK);
postcar_frame_add_mtrr(pcf, top_of_ram - 32 * MiB, 32 * MiB, MTRR_TYPE_WRBACK);
/* Cache the TSEG region */
postcar_enable_tseg_cache(pcf);