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soc/intel/pantherlake: Remove UFS support

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Unified Flash Storage (UFS) has been descoped from Panther Lake
configurations, limiting UFS functionality to Wildcat Lake. This change
removes Panther Lake's UFS configuration options and references,
ensuring proper alignment with the current product specifications.

BUG=b:442891168

Change-Id: Ib7e7498a57c8fbc924d6dcf70e374611733918c0
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88988
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
This commit is contained in:
Jeremy Compostella 2025-08-28 15:27:57 -07:00 • committed by Subrata Banik
commit 56dbafcff4
5 changed files with 5 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

1
src/soc/intel/pantherlake/Kconfig
View file

@ -453,6 +453,7 @@ config SOC_PHYSICAL_ADDRESS_WIDTH
config SOC_INTEL_UFS_CLK_FREQ_HZ
int
depends on SOC_INTEL_WILDCATLAKE
default 38400000
# Override DEBUG Kconfig to avoid false alarm about stack overflow.

2
src/soc/intel/pantherlake/acpi/southbridge.asl
View file

@ -54,6 +54,6 @@
#endif
/* UFS 0:17:0 */
#if (CONFIG(SOC_INTEL_PANTHERLAKE_U_H) || CONFIG(SOC_INTEL_WILDCATLAKE))
#if CONFIG(SOC_INTEL_WILDCATLAKE)
#include <soc/intel/common/block/acpi/acpi/ufs.asl>
#endif

1
src/soc/intel/pantherlake/chipset_ptl.cb
View file

@ -173,7 +173,6 @@ chip soc/intel/pantherlake
device pci 16.1 alias heci2 off end
device pci 16.4 alias heci3 off end
device pci 16.5 alias heci4 off end
device pci 17.0 alias ufs off end
device pci 18.0 alias eheci1 off end
device pci 18.1 alias eheci2 off end
device pci 18.2 alias eheci3 off end

4
src/soc/intel/pantherlake/fsp_params.c
View file

@ -212,7 +212,7 @@ static const struct slot_irq_constraints irq_constraints[] = {
ANY_PIRQ(PCI_DEVFN_CSE_4),
},
},
#if (CONFIG(SOC_INTEL_PANTHERLAKE_U_H) || CONFIG(SOC_INTEL_WILDCATLAKE))
#if (CONFIG(SOC_INTEL_WILDCATLAKE))
{
.slot = PCI_DEV_SLOT_UFS,
.fns = {
@ -741,7 +741,7 @@ static void fill_fsps_iax_params(FSP_S_CONFIG *s_cfg,
static void fill_fsps_ufs_params(FSP_S_CONFIG *s_cfg,
const struct soc_intel_pantherlake_config *config)
{
#if (CONFIG(SOC_INTEL_PANTHERLAKE_U_H) || CONFIG(SOC_INTEL_WILDCATLAKE))
#if CONFIG(SOC_INTEL_WILDCATLAKE)
/* Setting FSP UPD (1,0) to enable controller 0 */
s_cfg->UfsEnable[0] = is_devfn_enabled(PCI_DEVFN_UFS);
s_cfg->UfsEnable[1] = 0;

2
src/soc/intel/pantherlake/include/soc/pci_devs.h
View file

@ -150,7 +150,7 @@
#define PCI_DEV_CSE_3 _PCI_DEV(CSE, 4)
#define PCI_DEV_CSE_4 _PCI_DEV(CSE, 5)
#if (CONFIG(SOC_INTEL_PANTHERLAKE_U_H) || CONFIG(SOC_INTEL_WILDCATLAKE))
#if CONFIG(SOC_INTEL_WILDCATLAKE)
#define PCI_DEV_SLOT_UFS 0x17
#define PCI_DEVFN_UFS _PCI_DEVFN(UFS, 0)
#define PCI_DEV_UFS _PCI_DEV(UFS, 0)