Add a fw_config for touchscreen and non-touchscreen sku.
Based on the field to differentiat the touchscreen I2C port on/off
and GPIOs configuration.
BUG=none
TEST=Update the fw_config field and check the ap log:
ABSENCE = 0 ... without touchscreen i2c probing messages.
PRESENCE = 1 ... with touchscreen i2c probing messages.
Change-Id: I5f2cc0b0c37986240fbbeae3668ccc250748295d
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89851
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This change applies the same fix as coreboot change CB:89605 to the
kinmen variant. Without this change, headset jack detection won't work.
The original change 752d49a4ff was:
"mb/google/fatcat/var/moonstone: Disable RT721 clock stop support"
RT721 headset jack detection fails because the wakeup event is not
triggered during runtime suspend in D3 state. Disable the clock stop
to allow the bus driver to handle the wakeup process properly. The MIPI
Disco property is "mipi-sdw-simplified-clockstopprepare-sm-supported".
BUG=b:435094908
TEST=After plugging a headset, audio output is switched to it.
Change-Id: I468d949e1249548348493c070b4955c012ef7b4e
Signed-off-by: Norman Bintang <normanbt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89784
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Set the GPE0 registers (DW0, DW1, and DW2) to configure General
Purpose Events (GPEs) for the Lapis variant. This configures
GPP_VGPIO, GPP_F, and GPP_E as the Tier-1 PMC GPIO groups.
This patch ensures the variant can override the default baseboard
(fatcat) GPE settings, which may not align with the variant's
(aka lapis) hardware.
BUG=b:414614106
TEST=Able to override PMC GPEs as per google/lapis configuration.
Change-Id: Icd191d5265619ebfbf7f8dabb39a91a6517dfbd8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: hualin wei <weihualin@huaqin.corp-partner.google.com>
Configure the Touch Host Controller (THC) devices 0 and 1 on the
Fatcat/Lapis variant to use HID over I2C mode.
This change explicitly sets the thc_mode[0] and thc_mode[1] registers
to THC_HID_I2C_MODE in overridetree.cb. This is necessary to correctly
initialize the THC for devices like touchpads or touchscreens that
communicate using this protocol.
BUG=b:455442712
TEST=Able to build and boot google/lapis with functional touchpad.
Change-Id: I7c9a62afab396cb38775eaa5e96f2dc7ed773216
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89818
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Touch Host Controller (THC) requires its dedicated VGPIO pins to
remain enabled as a General Purpose Event (GPE) source for the system
to wake up on touch events.
This change introduces override_tier_1_gpio_chip_config to explicitly
check the thc_wake_on_touch status for each enabled THC interface.
If any wake-on-touch functionality is active, the Tier-1 GPE
configuration (pmc_gpe0_dw0) is overridden to ensure the GPP_VGPIO
bank is included.
This guarantees that the VGPIO pins dedicated to THC are always
monitored as a wake source when required by the platform
configuration.
BUG=b:414614106
TEST=Able to build and boot google/fatcat.
Change-Id: Ia1165c167850f5d66a8c5a85e3ec64f80e7a40da
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89817
Reviewed-by: Huang, Cliff <cliff.huang@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add stop pin control for G2 touchscreen.
BUG=b:456578327
TEST=build and verified Touchscreen work normally.
Change-Id: I0581fffdc2ec16a1c36b2e716b0fae27bad465ee
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89813
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Based on the Moonstone Schematic Proto 2.0 design, disable
Thunderbolt support for TCSS_PORT0 on the MB and TCSS_PORT1
on the DB.
Schematic: Kinmen(ZDQ)_Proto2.0_Moonstone_1014.pdf
BUG＝none
TEST=emerge-fatcat coreboot
Change-Id: Ie9acb9d68234b2d8bfc9392cf89d581de8c54a08
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89819
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable rp5 if the FW_CONFIG bits for WIFI are set to WIFI_PCIE_6 or
WIFI_PCIE_7.
BUG=b:444509417
TEST=emerge-ocelot coreboot chromeos-bootimage', flash ocelot and
verify CNVI and PCIe WiFi solutions are detected correctly.
Change-Id: I077bfc48a82c354d1011ef756aa6aa55bf6951cd
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
PCIe Root Port 5 uses both CLKSRC 1 and CLKSRC 2, but coreboot's
devicetree only allows configuring a single clock source per port. Add
a comment to document that CLKSRC 2 is implicitly used by the hardware.
Change-Id: I9b54d97fa5e4e4e80a58392a7592bab91e00824d
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This reverts commit 8a2c04e04d.
Reason for revert: The hang is still present
Change-Id: Iba3c2b684cce3adefecd175d0ef09a5d051410ae
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89805
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit 80861a9f69 ("mb/starlabs/starlite_adl: Add CFR option for
USB card reader") added support for the USB card reader, but did
not add the corresponding ACPI entries.
Change-Id: Ibef1b8412d5f51ffbfa715bb1ee80f73411dd3b3
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89772
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently wwan_power.asl clears gpio WWAN (PERST) during power-off.
Caboc project uses a MOS reverse pin to connect GPP_A21
(WWAN_ASPM_EXIT) to WWAN (PERST). Based on this design, uses STXS to
keep GPP_A21 high to meet power-off sequence.
Set T1_OFF_MS to 20ms and T2_OFF_MS to 10ms as HW engineer requested.
BUG=b:453512678
TEST=emerge-brox coreboot
HW enginer has measured and confirms WWAN power-off sequence.
Change-Id: I202a370dba2ba1dec61b1ad44140674bd470ba6e
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reconfigure I2C controller settings to disable I2C1 and enable I2C6
for the mc_rpl1 mainboard. This change reflects the updated hardware
configuration requirements.
Changes:
- Disable I2C controller 1
- Enable I2C controller 6
TEST=Build and boot tested on mc_rpl1 mainboard.
Verified I2C6 functionality and confirmed I2C1 is disabled with
`lspci -v | grep -A 5 "Serial bus controller"`. The output
confirms that I2C6 (PCI 00:10.0) is enabled and I2C1 (PCI 00:15.1)
is disabled because it is absent.
```
00:10.0 Serial bus controller: Intel Corporation Alder Lake-P Serial IO I2C Controller #2 (rev 01)
Subsystem: Intel Corporation Alder Lake-P Serial IO I2C Controller
Flags: bus master, fast devsel, latency 0, IRQ 24, IOMMU group 4
Memory at 80a12000 (64-bit, non-prefetchable) [size=4K]
Capabilities: [80] Power Management version 3
Capabilities: [90] Vendor Specific Information: Len=14 <?>
```
Change-Id: I4867062743ee10b34f94a1e588a10115b553a16e
Signed-off-by: Kilian Krause <kilian.krause@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89690
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Test=Change fan mode on byte_adl in edk2 and verify correct value
is written to the EC memory using `ectool -d`
Change-Id: I93d4be663a059abb973ad6abf2e60d40f56ed6c7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Pujjoga and pujjogatwin projects are both going to be single RAM device, so add single ram configuration.
Schematic version: 500E_GEN4S_ADL_N_MB_250920
Below log show the device can recognize the single dram.
[INFO ] SPD: module type is LPDDR5X
[INFO ] SPD: module part number is H9JCNNNBK3MLYR-N6E
[INFO ] SPD: banks 8, ranks 1, rows 16, columns 11, density 16384 Mb
[INFO ] SPD: device width 16 bits, bus width 16 bits
[INFO ] SPD: module size is 2048 MB (per channel)
[INFO ] Device only supports one DIMM. Disable all other memory
channels except first two on each memory controller.
[DEBUG] CBMEM:
[DEBUG] IMD: root @ 0x76fff000 254 entries.
[DEBUG] IMD: root @ 0x76ffec00 62 entries.
BUG=b:445629015
BRANCH=none
TEST=Build and boot to OS. Verify functions work.
Change-Id: I22e8335432e6e65bd1640bf6a6dec03691e3462e
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89221
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Increase the ME region by 4KiB to match the IFD that is used for
both the Alder Lake and Twin Lake versions.
Change-Id: I22fa2388ed5660b959815be00029c07cac2b5244
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89761
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch corrects the EC sync IRQ configuration logic to properly
handle different ocelot board variants:
1. Update conditional compilation in ec.h to exclude OCELOTMCHP and
OCELOTMCHP4ES variants from EC_ENABLE_SYNC_IRQ, as these boards do
not have the EC sync IRQ connected.
2. Restructure GPIO definitions in gpio.h to:
- Set EC_SYNC_IRQ to 0 (not connected) for OCELOTMCHP, OCELOTMCHP4ES,
variants.
- Enable EC_SYNC_IRQ on GPP_E08_IRQ for OCELOT, OCELOT4ES, OCELOTITE,
and OCELOTITE4ES variants.
3. Configure GPP_E08 pad appropriately in gpio.c:
- Set as NC (not connected) for OCELOTMCHP variants.
- Configure as APIC interrupt for other variants that support EC sync
IRQ functionality.
BUG=NONE
TEST=Build and boot on Ocelot variants.
Change-Id: I96e92ed9d6fa5b586ab9c0faf73d08b55abe4795
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89459
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reduce reset delay from 20ms to 0ms to shorten total tp_rst time from
350ms to 330ms. Validation on Prade shows the controller initializes
reliably within the reduced timing. It will be able to complete the
following steps before vccs on.
1. TP Reset
2. Get HID Description
3. HID Reset/HID Power On
4. Get Report Descriptor/Get Feature Report
Verification results are in b/455053468 comment#3
BUG=b:455053468
BRANCH=none
TEST=Build and boot to pujjocento. Verify touchpanel sequence
Change-Id: I4efa4e927e78d3200b357f5f5b41c3d2aef12f8b
Signed-off-by: Zheng Li <lizheng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89748
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Commit 7d8e105420 ("mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge
board GA-H77M-D3H"), adding this board, initially enabled igd and
peg10 in the device tree, but later, during review, Patchset 10
removed those lines of the device tree entirely, disabling onboard
and PCIe graphics in the port as ultimately submitted.
This commit re-adds these lines to the device tree, enabling both -
thanks to nic3-14159 for spotting the issue. I have confirmed both
now work on my GA-H77M-D3H.
TEST=Confirm IGD outputs as configured in SeaBIOS and Linux (with
CONFIG_ONBOARD_VGA_IS_PRIMARY), same for PCIe GPU (running option
ROMs).
$ lspci
00:00.0 Host bridge: Intel Corporation Xeon E3-1200 v2/3rd Gen Core
processor DRAM Controller (rev 09)
00:02.0 VGA compatible controller: Intel Corporation Xeon E3-1200
v2/3rd Gen Core processor Graphics Controller (rev 09)
...
With a monitor connected to the onboard DVI:
$ cat /sys/class/graphics/fb0/virtual_size
1920,1080
Change-Id: I248827b92d9f14cedbbd666d533764b5f152cf29
Signed-off-by: Dodoid <git-noreply@dodoid.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
New port based on logs extracted from a board running OEM firmware.
VBT extracted from a running system with "intelvbttool --inlegacy".
Internal flashing of the entire chip is possible from vendor firmware
by overriding the Flash Descriptor. Conveniently, the HDA_SDO pin is
connected to one of the unused pins of the PCIE1 slot.
Tested:
- i7-3770K CPU (native raminit)
- 2x8GB: G.skill F3-1600C9-8GAR (@1600MHz)
- 4x8GB: Corsair CMY16GX3M2A2400C (@1333MHz)
- libgfxinit txtmode with onboard HDMI, DVI and VGA
- Gigabit Ethernet
- CPU fan
- PS/2 keyboard or mouse (but not at the same time)
- SeaBIOS 1.17.0 booting to Devuan and Void Linux
- All internal SATA ports
- Rear USB ports
- Line out
- me_cleaner
- PCIE2 (x16/x8), PCIE3 (x8) and PCIE4 (x1) slots
- PCI slots
- Suspend and resume (S3)
- Serial port header COM1 (including coreboot output)
Untested:
- Intel VBIOS
- Front USB headers
- Other fans
- LED headers
- eSATA, Toslink
- PCIE1 (x1) slot
Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add firmware configuration support for SPD (Serial Presence Detect)
selection on Intel PTLRVP boards. This change allows dynamic memory
configuration based on fw_config fields instead of relying solely on
board ID detection.
BUG=None
TEST=Build and verify SPD selection works correctly on PTLRVP boards
with different memory configurations.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I3cc45ad9813bef09718fe679bfafb700024586f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/88255
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The hardware is mostly identical to the already supported Thinkpad
T480s. Aside from the CPU (KBL vs SKL), major hardware differences are
GPIO pins routed out to a classical docking station connector, and the
lack of support for dedicated GPUs.
A tricky aspect of this machine is that it fails to enumerate PCIe
devices when using a truncated Intel ME firmware even when retaining
the MFS partition [1]. I suspect that the PCIe clock generators are set
up in some other part of the ME firmware.
The VBT (intelvbttool) as well as GPIO register dumps (inteltool) was
obtained from the latest stock BIOS 1.55/N1WET76W. GPIO, USB and PCIe
port assignments have been cross-checked against the publicly available
schematics (Thorpe-2).
The patches were validated on a laptop with part number 20JT-S16E00 in
conjunction with a non-truncated deguarded Intel ME firmware [2].
A cursory hardware test (video, wifi, audio, network, reboot, etc.) has
everything working as expected (debian 13).
[1] https://puri.sm/posts/deep-dive-into-intel-me-disablement/
[2] deguard commit 497732f8b2e3bdc699c0fbc6713b6afbaef7506a
Change-Id: I113b31484a634b7c1acdba5f74e5eef050d4ede6
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89638
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Create the kodkod variant of the ocelot reference board by copying
the ocelot files to a new directory named for the variant.
BUG=b:451760650
TEST=util/abuild/abuild -p none -t google/ocelot -x -a
make sure the build includes GOOGLE_KODKOD
Change-Id: I8bbea4444d65e57b98bf9c8a621ff548abb8aece
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89679
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a legacy option that changed the charging frequency. It
is no longer needed as the "normal" frequency is faster and more
stable so remove it.
Change-Id: I73cf439d96d65f0be26595e42a4aedbc4388b850
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
1. Add DB_1C_5G 8 on DB_USB overridetree.
2. Also disable LTE-related GPIOs based on fw_config when system
was DB_1C_5G.
BUG=b:445338278
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Check 5G LTE module detectable by command # mmcli -m a.
Change-Id: I3d525d9de151427d38485882117b59939b9da5c7
Signed-off-by: Joyce Ciou <Joyce_Ciou@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89606
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
RT721 headset jack detection fails because the wakeup event is not
triggered during runtime suspend in D3 state. Disable the clock stop
to allow the bus driver to handle the wakeup process properly. The MIPI
Disco property is "mipi-sdw-simplified-clockstopprepare-sm-supported".
BUG= b:435094908
TEST= verify headset jack works properly.
Change-Id: Ibd5271e496a9ca841498b17a5746e300f9557078
Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89605
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch increases the size of the FW_MAIN_A and FW_MAIN_B slots to
4608KB (4.5MB) to incorporate the QTEE FW and its config files.
TEST =Create an image.serial.bin and ensure it boots on X1P42100.
Change-Id: I69ce0f3cff2cae110a21417245c425ee8bcf1e6c
Signed-off-by: Venkateshwar S <vens@qualcomm.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89549
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Now that the PinMux is correctly configured, everything works
as it should without having FSP touch the GPIOs.
Change-Id: Ieec678594f49f3aa003ade29aad85b24ec03f1ad
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
We use winbond, gigadevice spi flash, and will use spi flash from other vendors in the future, so we have enable all SPI Flash drivers.
BUG=b:442967024
BRANCH=None
TEST=emerge-bluey coreboot chromeos-bootimage
Change-Id: Icb9eeea90e924d412ad782ccf1ac390707f27314
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89641
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add initial thermal settings
- Remove fan control (handled by EC)
- Apply PL1/PL2 min & max values per thermal design
BUG=b:446813859
TEST=emerge-fatcat coreboot
Change-Id: I193951036abb9a37af6583de0b1401501524b2d8
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
None of these boards strictly "need" an ITE binary, so remove the
Kconfig option. This leaves the logic to add a binary untouched,
so it can be added if desired.
Change-Id: I6cd674a794cac51900b9a11c434b25e28a052b6a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89645
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adjust fingerprint power sequence to let the time interval between PP3300_MCU and MCU_RST_ODL H(GPP_E7) is 5.1ms(before is 1.1s), meet spec 5.95ms.
BUG=b:411558536
BRANCH=none
TEST=Build and boot to OS. Verify fingerprint power sequence by
EE colleagues.
Change-Id: Ic93af108144a3f227024a8749e0cf88b2f2d90ff
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Select HAVE_ACPI_TABLES & PCI for QEMU riscv virt machine mainboard. Add
an empty dsdt.asl to fit current build process, but it will not actually
be used since QEMU has its own method of providing DSDT blob.
TEST=build and run successfully on QEMU rvvirt machine. Using command
"qemu-system-riscv64 -machine virt,aia=aplic-imsic,acpi=on -bios
build/coreboot.rom -nographic -pflash build/coreboot.rom".
Change-Id: If8c9b5d86adb69afdcb4bf320d6353b2b2acfb31
Signed-off-by: Ziang Wang <wangziang.ok@bytedance.com>
Signed-off-by: Dong Wei <weidong.wd@bytedance.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89562
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the CS42L43 codec on SoundWire link 3 and the CS35L56
amplifiers on SoundWire link 2.
Scope (\_SB.PCI0.HDAS.SNDW)
{
Device (SW30)
{
Name (_ADR, 0x00033001FA424301) // _ADR: Address
Name (_DDN, "Headset Codec") // _DDN: DOS Device Name
Name (_SUB, "1337") // _SUB: Subsystem ID
...
{
Device (SW20)
{
Name (_ADR, 0x00023001FA355601) // _ADR: Address
Name (_DDN, "Left Speaker Amp") // _DDN: DOS Device Name
Name (_SUB, "12345678") // _SUB: Subsystem ID
...
Device (SW21)
{
Name (_ADR, 0x00023101FA355601) // _ADR: Address
Name (_DDN, "Right Speaker Amp") // _DDN: DOS Device Name
Name (_SUB, "12345678") // _SUB: Subsystem ID
...
BUG=b:444122406, b:444302600
TES=emerge-lapis coreboot
Change-Id: Ic73d705655bdc0a4a8140feafa28aceb2fc25ad3
Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89345
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Originally, there were separate EC firmware builds for the smart
battery (SB) and non-SB versions of the starlite_adl board, but those
have long since been unified. Squash the board variants into a single
board which supports both SB and non-SB boards.
Adjust the board description to reflect that it will support both the
existing N200 and upcoming N355 flavors.
TEST=build/boot starlite_adl on both SB and non-SB boards, verify
battery and all other features function normally.
Change-Id: I2461a094f2455ce333132ffa9f2f83967ae0e927
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Add a CFR setup menu option to enable/disable the USB micro-SD card
reader, but restrict it to newer boards which use the MXC
accelerometer, as those boards have the card reader on USB2 port 4,
rather than shared with the detachable keyboard on port 3.
TEST=build/boot on starlite_adl boards with and without the MXC
accelerometer, verify only boards with it have the CFR option
to disable the card reader shown, and that the option works
as expected.
Change-Id: I9255d008c6f322d01390ed9f19e4e963cf04eeb6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Create the ruby variant of the fatcat reference board by copying
the fatcat files to a new directory named for the variant.
BUG=b:446771934
TEST=1. util/abuild/abuild -p none -t google/fatcat -x -a
make sure the build includes GOOGLE_RUBY
2. Run part_id_gen tool without any errors
Change-Id: Ie5f4a152d792f241a0044f18653b5363e1637b49
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89327
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
During Uldrenite development, the ISH UART port design and VR settings
were changed, so the switching mechanism was implemented based on the
board ID. Uldrino adopts the latest Uldrenite design; however, its
board ID starts from 0. To resolve this issue, an additional FW_CONFIG
field is added to further distinguish between Uldrenite and Uldrino.
BUG=b:450182476
TEST=Verified the ISH log and used the servod board to dump the CPU
log for checking PMC Descriptor Record 7 at offset 0xC33.
Change-Id: Id24659d6f910de1d3da36c5da808fd768dbdbc37
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89457
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Due to only 1A on DB, the test item of FAFT EC
firmware.DevInsertUSBScreen.insert_usb would be captured much error
message to detect C1 if set the flag.
And then missed to capture the correct message when running the test.
Therefore, removed the DB_1A for pmc_mux on daughter board to fix
the issue.
BUG=b:451436640
TEST=USE="${USE} -project_all project_craaskyu2" emerge-nirva \
coreboot chromeos-zephyr chromeos-bootimage
Confirm firmware.DevInsertUSBScreen.insert_usb PASS.
Change-Id: I6b1a3c99d422c99103818556365b0e5929a18dbf
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89538
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Issue=ACP is not active in S3 state and audio playback doesnt work
Fix=Introduce a config option to control this setting.
TEST=Tested this in ACPI S3 state,by connecting an external CODEC and
transmitting a known pattern to the ACP via the I2S TDM controller RX
lines and ensuring that the sound is output to the speaker connected
to the CODEC via the TDM TX line.
Change-Id: Ifbd3e72a4d018e4a14d9459dd3a6804dd27050e4
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89610
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
