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mb/google/fatcat/var/moonstone: Enable Intel DPTF support

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Add initial thermal settings
- Remove fan control (handled by EC)
- Apply PL1/PL2 min & max values per thermal design

BUG=b:446813859
TEST=emerge-fatcat coreboot

Change-Id: I193951036abb9a37af6583de0b1401501524b2d8
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
This commit is contained in:
Ren Kuo 2025-10-16 18:43:15 +08:00 • committed by Matt DeVillier
commit f6743fba29
1 changed files with 93 additions and 0 deletions
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93
src/mainboard/google/fatcat/variants/moonstone/overridetree.cb
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@ -123,6 +123,99 @@ chip soc/intel/pantherlake
end
end
device ref dtt on
chip drivers/intel/dptf
## sensor information
register "options.tsr[0].desc" = ""DDR_SOC""
register "options.tsr[1].desc" = ""Ambient""
register "options.tsr[2].desc" = ""Charger""
## Active Policy
# FIXME: below values are initial reference values only
register "policies.active" = "{
[0] = {
.target = DPTF_TEMP_SENSOR_0,
.thresholds = {
TEMP_PCT(70, 97),
TEMP_PCT(65, 90),
TEMP_PCT(60, 80),
TEMP_PCT(55, 75),
TEMP_PCT(50, 65),
TEMP_PCT(45, 45),
TEMP_PCT(43, 30),
}
},
[1] = {
.target = DPTF_TEMP_SENSOR_1,
.thresholds = {
TEMP_PCT(70, 97),
TEMP_PCT(65, 90),
TEMP_PCT(60, 80),
TEMP_PCT(55, 75),
TEMP_PCT(50, 65),
TEMP_PCT(45, 45),
TEMP_PCT(43, 30),
}
},
[2] = {
.target = DPTF_TEMP_SENSOR_2,
.thresholds = {
TEMP_PCT(75, 90),
TEMP_PCT(70, 80),
TEMP_PCT(65, 70),
TEMP_PCT(60, 50),
}
}
}"
## Passive Policy
# TODO: below values are initial reference values only
register "policies.passive" = "{
[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 5000),
[2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 80, 5000),
[3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 5000),
}"
## Critical Policy
# TODO: below values are initial reference values only
register "policies.critical" = "{
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN),
[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN),
[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 85, SHUTDOWN),
}"
## Power Limits Control
register "controls.power_limits" = "{
.pl1 = {
.min_power = 12000,
.max_power = 15000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 200,
},
.pl2 = {
.min_power = 55000,
.max_power = 55000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,
.granularity = 1000,
}
}"
## Charger Performance Control (Control, mA)
register "controls.charger_perf" = "{
[0] = { 255, 3000 },
[1] = { 24, 1500 },
[2] = { 16, 1000 },
[3] = { 8, 500 }
}"
device generic 0 alias dptf_policy on end
end
end
device ref iaa off end
device ref tbt_pcie_rp0 on end
device ref tbt_pcie_rp1 on