mb/nissa/var/pujjoga: Add single ram configuration

Pujjoga and pujjogatwin projects are both going to be single RAM device, so add single ram configuration.

Schematic version: 500E_GEN4S_ADL_N_MB_250920

Below log show the device can recognize the single dram.
[INFO ]  SPD: module type is LPDDR5X
[INFO ]  SPD: module part number is H9JCNNNBK3MLYR-N6E
[INFO ]  SPD: banks 8, ranks 1, rows 16, columns 11, density 16384 Mb
[INFO ]  SPD: device width 16 bits, bus width 16 bits
[INFO ]  SPD: module size is 2048 MB (per channel)
[INFO ]  Device only supports one DIMM. Disable all other memory
channels except first two on each memory controller.
[DEBUG]  CBMEM:
[DEBUG]  IMD: root @ 0x76fff000 254 entries.
[DEBUG]  IMD: root @ 0x76ffec00 62 entries.

BUG=b:445629015
BRANCH=none
TEST=Build and boot to OS. Verify functions work.

Change-Id: I22e8335432e6e65bd1640bf6a6dec03691e3462e
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89221
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/brya/Kconfig

@@ -491,6 +491,7 @@ config BOARD_GOOGLE_PUJJOGA
 	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select DRIVERS_I2C_SX9324
 	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
+	select ENFORCE_MEM_CHANNEL_DISABLE
 	select HAVE_WWAN_POWER_SEQUENCE
 	select INTEL_GMA_HAVE_VBT
 
@@ -500,6 +501,7 @@ config BOARD_GOOGLE_PUJJOGATWIN
 	select CHROMEOS_WIFI_SAR if CHROMEOS
 	select DRIVERS_I2C_SX9324
 	select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER
+	select ENFORCE_MEM_CHANNEL_DISABLE
 	select HAVE_WWAN_POWER_SEQUENCE
 	select INTEL_GMA_HAVE_VBT
 	select SOC_INTEL_TWINLAKE

src/mainboard/google/brya/variants/pujjoga/Makefile.mk

@@ -2,6 +2,7 @@
 bootblock-y += gpio.c
 
 romstage-y += gpio.c
+romstage-y += memory.c
 
 ramstage-$(CONFIG_FW_CONFIG) += fw_config.c
 ramstage-y += variant.c

src/mainboard/google/brya/variants/pujjoga/gpio.c

@@ -32,6 +32,8 @@ static const struct pad_config override_gpio_table[] = {
 	PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
 	/* D17 : NC ==> SD_WAKE_N */
 	PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG),
+	/* E9  : NC ==> DIMM_CHANNEL_SELECT */
+	PAD_CFG_GPI_LOCK(GPP_E9, DN_20K, LOCK_CONFIG),
 	/* E20  : NC */
 	PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG),
 	/* E21  : NC */
@@ -66,6 +68,8 @@ static const struct pad_config early_gpio_table[] = {
 	*/
 	/* D6  : SRCCLKREQ1# ==> WWAN_EN */
 	PAD_CFG_GPO(GPP_D6, 0, DEEP),
+	/* E9  : NC ==> DIMM_CHANNEL_SELECT */
+	PAD_CFG_GPI_LOCK(GPP_E9, DN_20K, LOCK_CONFIG),
 	/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
 	PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
 	/* F12 : WWAN_RST_L */

src/mainboard/google/brya/variants/pujjoga/memory.c

@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+uint8_t mb_get_channel_disable_mask(void)
+{
+	/*
+	 * GPP_E9 High -> Single RAM Chip
+	 * GPP_E9 Low  -> Dual RAM Chip
+	 */
+	if (gpio_get(GPP_E9)) {
+		/* Disable all other channels except first two on each controller */
+		printk(BIOS_INFO, "Device only supports one DIMM. Disable all other memory"
+		"channels except first two on each memory controller.\n");
+		return (BIT(2) | BIT(3));
+	}
+	return 0;
+
+}