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mb/nissa/var/pujjoquince: Modify fingerprint configuration

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Adjust fingerprint power sequence to let the time interval between PP3300_MCU and MCU_RST_ODL H(GPP_E7) is 5.1ms(before is 1.1s), meet spec 5.95ms.

BUG=b:411558536
BRANCH=none
TEST=Build and boot to OS. Verify fingerprint power sequence by
EE colleagues.

Change-Id: Ic93af108144a3f227024a8749e0cf88b2f2d90ff
Signed-off-by: Luca Lai <luca.lai@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
This commit is contained in:
Luca Lai 2025-10-20 16:40:49 +08:00 • committed by Subrata Banik
commit 7376761bdf
2 changed files with 8 additions and 22 deletions
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28
src/mainboard/google/brya/variants/pujjolo/gpio.c
View file

@ -169,7 +169,7 @@ static const struct pad_config override_gpio_table[] = {
/* E6 : THC0_SPI1_RST# ==> GPP_E6_STRAP */
PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG),
/* E7 : NC ==> FP_RST_ODL */
PAD_CFG_GPO_LOCK(GPP_E7, 1, LOCK_CONFIG),
PAD_CFG_GPO_LOCK(GPP_E7, 0, LOCK_CONFIG),
/* E8 : GPP_E8 ==> WLAN_DISABLE_L */
PAD_CFG_GPO(GPP_E8, 1, DEEP),
/* E9 : NC ==> DIMM_CHANNEL_SELECT */
@ -428,17 +428,10 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPO(GPP_D6, 0, DEEP),
/* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
/*
* E7 ==> FP_RST_ODL
* FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
* To ensure proper power sequencing for the FPMCU device, reset signal is driven low
* early on in bootblock, followed by enabling of power. Reset signal is deasserted
* later on in ramstage. Since reset signal is asserted in bootblock, it results in
* FPMCU not working after a S3 resume. This is a known issue.
*/
/* E7 ==> FP_RST_ODL */
PAD_CFG_GPO(GPP_E7, 0, DEEP),
/* D2 : ISH_GP2 ==> EN_FP_PWR */
PAD_CFG_GPO(GPP_D2, 1, DEEP),
PAD_CFG_GPO(GPP_D2, 0, DEEP),
/* E9 : DIMM_CHANNEL_SELECT */
PAD_CFG_GPI_LOCK(GPP_E9, DN_20K, LOCK_CONFIG),
/* E17 : WWAN_RST_L */
@ -466,17 +459,10 @@ static const struct pad_config romstage_gpio_table[] = {
PAD_CFG_GPO(GPP_C0, 1, DEEP),
/* C1 : SMBDATA ==> USI_RST_L */
PAD_CFG_TERM_GPO(GPP_C1, 0, UP_20K, DEEP),
/*
* E7 ==> FP_RST_ODL
* FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
* To ensure proper power sequencing for the FPMCU device, reset signal is driven low
* early on in bootblock, followed by enabling of power. Reset signal is deasserted
* later on in ramstage. Since reset signal is asserted in bootblock, it results in
* FPMCU not working after a S3 resume. This is a known issue.
*/
PAD_CFG_GPO(GPP_E7, 0, DEEP),
/* D2 : ISH_GP2 ==> EN_FP_PWR */
PAD_CFG_GPO(GPP_D2, 0, DEEP),
/* E7 ==> FP_RST_ODL */
PAD_CFG_GPO(GPP_E7, 0, DEEP),
/* D2 : ISH_GP2 ==> EN_FP_PWR */
PAD_CFG_GPO(GPP_D2, 0, DEEP),
/* H12 : UART0_RTS# ==> SD_PERST_L */
PAD_CFG_GPO(GPP_H12, 1, DEEP),
};

2
src/mainboard/google/brya/variants/pujjolo/overridetree.cb
View file

@ -733,7 +733,7 @@ chip soc/intel/alderlake
register "has_power_resource" = "1"
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)"
register "enable_delay_ms" = "3"
register "enable_delay_ms" = "10"
device spi 0 on
probe FP FP_PRESENT
end