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mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H

Browse source 
This board is based off ga-b75m-d3h, which uses the same SuperIO chip.
It doesn't have the ASMedia SATA3 controller, the H77 chipset comes with
2 SATA3 ports next to the 4 SATA2 ports.

Flashing notes:
  These boards come with dual-BIOS feature.  This is set of two
  unremovable what appears to be identical chips marked M_BIOS and
  B_BIOS.  Flash the B_BIOS chip, and boot the system.  Ensure you have
  a payload and setup ready to boot a Linux system with iomem=relaxed or
  similar.  Immediately use flashrom -p internal to flash the same
  firmware again.  If you skip this step your next boot will show weird
  exception traces in either coreboot or your payload.  Flashing from
  there via the chip is very difficult (you have to try many times in
  order to get a booting run), which can all be remedied by doing a
  flash from internal.  I suppose the dual-BIOS feature is somewhat in
  the way here.

Tested with:
- CPU Core i7-3770S
- RAM single bank 4GB CL11, two banks 4+4GB CL11
- OS Gentoo Linux LiveUSB, KDE desktop (Linux 5.15.72)

Working:
- GRUB2 payload
- Intel ME stripped
- Integrated graphics with libgfxinit
- (boot from) SATA2, SATA3 ports
- Rear and mainboard connector USB ports, supporting boot
- Atheros GbE NIC
- 2.0 channel audio via lineout jack output
- ACPI (power button triggers OS events)
- S3 suspend/resume
- PWM FAN control, FAN speed readings
- Temperature sensor readings

Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Change-Id: Icb3e74326a0a7aaf770d1917a2a0931feadd7eab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77046
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Fabian Groffen 2023-10-31 09:00:10 +01:00 • committed by Felix Singer
commit 7d8e105420
17 changed files with 565 additions and 0 deletions
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37
src/mainboard/gigabyte/ga-h77m-d3h/Kconfig Normal file
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## SPDX-License-Identifier: GPL-2.0-only
if BOARD_GIGABYTE_GA_H77M_D3H
config BOARD_SPECIFIC_OPTIONS
def_bool y
select NORTHBRIDGE_INTEL_SANDYBRIDGE
select USE_NATIVE_RAMINIT
select SOUTHBRIDGE_INTEL_C216
select SUPERIO_ITE_IT8728F
select BOARD_ROMSIZE_KB_8192
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select HAVE_ACPI_RESUME
select INTEL_GMA_HAVE_VBT
select SERIRQ_CONTINUOUS_MODE
select MAINBOARD_HAS_LIBGFXINIT
select MEMORY_MAPPED_TPM
config DRAM_RESET_GATE_GPIO
int
# Use GPIO25 because it does not exist on desktop PCHs and because
# this board does not use DRAM reset gate GPIO
default 25
config USBDEBUG_HCD_INDEX
int
default 2
config MAINBOARD_DIR
default "gigabyte/ga-h77m-d3h"
config MAINBOARD_PART_NUMBER
default "GA-H77M-D3H"
endif # BOARD_GIGABYTE_GA_H77_D3H

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src/mainboard/gigabyte/ga-h77m-d3h/Kconfig.name Normal file
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## SPDX-License-Identifier: GPL-2.0-only
config BOARD_GIGABYTE_GA_H77M_D3H
bool "GA-H77M-D3H"

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src/mainboard/gigabyte/ga-h77m-d3h/Makefile.mk Normal file
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## SPDX-License-Identifier: GPL-2.0-only
bootblock-y += gpio.c
romstage-y += gpio.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
bootblock-y += early_init.c
romstage-y += early_init.c

3
src/mainboard/gigabyte/ga-h77m-d3h/acpi/ec.asl Normal file
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/* SPDX-License-Identifier: CC-PDDC */
/* Please update the license if adding licensable material. */

16
src/mainboard/gigabyte/ga-h77m-d3h/acpi/platform.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
/* The _PTS method (Prepare To Sleep) is called before the OS is
* entering a sleep state. The sleep state number is passed in Arg0
*/
Method (_PTS, 1)
{
}
/* The _WAK method is called on system wakeup */
Method(_WAK,1)
{
Return (Package () {0, 0})
}

3
src/mainboard/gigabyte/ga-h77m-d3h/acpi/superio.asl Normal file
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/* SPDX-License-Identifier: CC-PDDC */
/* Please update the license if adding licensable material. */

7
src/mainboard/gigabyte/ga-h77m-d3h/board_info.txt Normal file
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Category: desktop
Board URL: https://www.gigabyte.com/Motherboard/GA-H77M-D3H-rev-10
ROM package: SOIC-8
ROM protocol: SPI
ROM socketed: n
Flashrom support: y
Release year: 2012

6
src/mainboard/gigabyte/ga-h77m-d3h/cmos.default Normal file
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boot_option=Fallback
debug_level=Debug
power_on_after_fail=Enable
nmi=Enable
sata_mode=AHCI
gfx_uma_size=32M

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src/mainboard/gigabyte/ga-h77m-d3h/cmos.layout Normal file
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## SPDX-License-Identifier: GPL-2.0-only
# -----------------------------------------------------------------
entries
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
395 4 e 6 debug_level
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
421 1 e 9 sata_mode
# coreboot config options: cpu
# coreboot config options: northbridge
432 3 e 11 gfx_uma_size
# coreboot config options: check sums
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
9 0 AHCI
9 1 IDE
11 0 32M
11 1 64M
11 2 96M
11 3 128M
11 4 160M
11 5 192M
11 6 224M
# -----------------------------------------------------------------
checksums
checksum 392 439 984

BIN
src/mainboard/gigabyte/ga-h77m-d3h/data.vbt Normal file
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Binary file not shown.

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src/mainboard/gigabyte/ga-h77m-d3h/devicetree.cb Normal file
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## SPDX-License-Identifier: GPL-2.0-only
chip northbridge/intel/sandybridge
register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}"
device domain 0 on
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
register "gen1_dec" = "0x003c0a01"
# Set max SATA speed to 6.0 Gb/s
register "sata_port_map" = "0x3f"
register "sata_interface_speed_support" = "0x3"
register "usb_port_config" = "{
{ 1, 5, 0 },
{ 1, 5, 0 },
{ 1, 5, 1 },
{ 1, 5, 1 },
{ 1, 5, 2 },
{ 1, 5, 2 },
{ 1, 5, 3 },
{ 1, 5, 3 },
{ 1, 5, 4 },
{ 1, 5, 4 },
{ 1, 5, 6 },
{ 1, 5, 5 },
{ 1, 5, 5 },
{ 1, 5, 6 }
}"
register "xhci_switchable_ports" = "0xf"
register "superspeed_capable_ports" = "0xf"
device ref xhci on # USB 3.0 Controller
subsystemid 0x1458 0x5007
end
device ref mei1 off end # Management Engine Interface 1
device ref ehci2 on # USB2 EHCI #2
subsystemid 0x1458 0x5006
end
device ref hda on # High Definition Audio
subsystemid 0x1458 0xa002
end
device ref pcie_rp1 on end # PCIe Port #1: PCIEX4 slot
device ref pcie_rp2 off end # PCIe Port #2
device ref pcie_rp3 off end # PCIe Port #3
device ref pcie_rp4 off end # PCIe Port #4
device ref pcie_rp5 on # PCIe Port #5: AR8161 GbE
device pci 00.0 on end
end
device ref pcie_rp6 on end # PCIe Port #6: PCIEX1 slot
device ref pcie_rp7 on end # PCIe Port #7: IT8892E PCIe-to-PCI
device ref pcie_rp8 off end # PCIe Port #8
device ref ehci1 on # USB2 EHCI #1
subsystemid 0x1458 0x5006
end
device ref pci_bridge off end # PCI bridge
device ref lpc on # ISA/LPC bridge
subsystemid 0x1458 0x5001
chip superio/ite/it8728f
register "TMPIN1.mode" = "THERMAL_RESISTOR"
register "TMPIN1.min" = "-10"
register "TMPIN1.max" = "100"
register "TMPIN2.mode" = "THERMAL_MODE_DISABLED"
register "TMPIN3.mode" = "THERMAL_PECI"
register "TMPIN3.offset" = "100"
register "TMPIN3.min" = "0"
register "TMPIN3.max" = "100"
register "ec.vin_mask" = "VIN7 | VIN4 | VIN3 | VIN2 | VIN1 | VIN0"
device pnp 2e.0 off end # FDC
device pnp 2e.1 on # Serial Port 1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.2 on
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.3 on
io 0x60 = 0x378
irq 0x70 = 7
drq 0x74 = 4
end
device pnp 2e.4 on # EC
io 0x60 = 0xa30
irq 0x70 = 9
io 0x62 = 0xa20
end
device pnp 2e.5 on # Keyboard
io 0x60 = 0x60
irq 0x70 = 1
io 0x62 = 0x64
end
device pnp 2e.6 on # Mouse
irq 0x70 = 12
end
device pnp 2e.7 off end # GPIO
device pnp 2e.a off end # IR
end
chip drivers/pc80/tpm
device pnp 0c31.0 off end
end
end
device ref sata1 on # SATA Controller 1
subsystemid 0x1458 0xb005
end
device ref smbus on # SMBus
subsystemid 0x1458 0x5001
end
device ref sata2 off end # SATA Controller 2
end
end
end

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src/mainboard/gigabyte/ga-h77m-d3h/dsdt.asl Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
DefinitionBlock(
"dsdt.aml",
"DSDT",
ACPI_DSDT_REV_2,
OEM_ID,
ACPI_TABLE_CREATOR,
0x20141018
)
{
#include <acpi/dsdt_top.asl>
#include <southbridge/intel/common/acpi/platform.asl>
#include "acpi/platform.asl"
#include <cpu/intel/common/acpi/cpu.asl>
/* global NVS and variables. */
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <southbridge/intel/common/acpi/sleepstates.asl>
Scope (\_SB) {
Device (PCI0)
{
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
}
}
}

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src/mainboard/gigabyte/ga-h77m-d3h/early_init.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h>
#include <superio/ite/common/ite.h>
#include <superio/ite/it8728f/it8728f.h>
#define SUPERIO_BASE 0x2e
#define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO)
#define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01)
void bootblock_mainboard_early_init(void)
{
/* Initialize SuperIO */
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
ite_reg_write(SIO_GPIO, 0xEF, 0x7E); // magic SIO disable reboot
/* FIXME: These values could be configured in ramstage */
ite_reg_write(SIO_GPIO, 0x25, 0x40); // gpio pin function -> gp16
ite_reg_write(SIO_GPIO, 0x27, 0x10); // gpio pin function -> gp34
ite_reg_write(SIO_GPIO, 0x2c, 0x80); // smbus isolation on parallel port
ite_reg_write(SIO_GPIO, 0x62, 0x0a); // simple iobase 0xa00
ite_reg_write(SIO_GPIO, 0x72, 0x20); // watchdog timeout clear!
ite_reg_write(SIO_GPIO, 0x73, 0x00); // watchdog timeout clear!
ite_reg_write(SIO_GPIO, 0xcb, 0x00); // simple io set4 direction -> in
ite_reg_write(SIO_GPIO, 0xe9, 0x27); // bus select disable
ite_reg_write(SIO_GPIO, 0xf0, 0x10); // ?
ite_reg_write(SIO_GPIO, 0xf1, 0x42); // ?
ite_reg_write(SIO_GPIO, 0xf6, 0x1c); // hwmon alert beep -> gp36(pin12)
/* EC SIO settings */
ite_reg_write(IT8728F_EC, 0xf1, 0xc0);
ite_reg_write(IT8728F_EC, 0xf6, 0xf0);
ite_reg_write(IT8728F_EC, 0xf9, 0x48);
ite_reg_write(IT8728F_EC, 0x60, 0x0a);
ite_reg_write(IT8728F_EC, 0x61, 0x30);
ite_reg_write(IT8728F_EC, 0x62, 0x0a);
ite_reg_write(IT8728F_EC, 0x63, 0x20);
ite_reg_write(IT8728F_EC, 0x30, 0x01);
}

17
src/mainboard/gigabyte/ga-h77m-d3h/gma-mainboard.ads Normal file
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-- SPDX-License-Identifier: GPL-2.0-only
with HW.GFX.GMA;
with HW.GFX.GMA.Display_Probing;
use HW.GFX.GMA;
use HW.GFX.GMA.Display_Probing;
private package GMA.Mainboard is
ports : constant Port_List :=
(HDMI1,
HDMI3,
Analog,
others => Disabled);
end GMA.Mainboard;

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src/mainboard/gigabyte/ga-h77m-d3h/gpio.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <southbridge/intel/common/gpio.h>
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio12 = GPIO_MODE_GPIO,
.gpio25 = GPIO_MODE_GPIO,
};
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
.gpio30 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio0 = GPIO_LEVEL_HIGH,
.gpio1 = GPIO_LEVEL_HIGH,
.gpio2 = GPIO_LEVEL_HIGH,
.gpio3 = GPIO_LEVEL_HIGH,
.gpio4 = GPIO_LEVEL_HIGH,
.gpio5 = GPIO_LEVEL_HIGH,
.gpio6 = GPIO_LEVEL_HIGH,
.gpio7 = GPIO_LEVEL_HIGH,
.gpio9 = GPIO_LEVEL_HIGH,
.gpio10 = GPIO_LEVEL_HIGH,
.gpio11 = GPIO_LEVEL_HIGH,
.gpio12 = GPIO_LEVEL_HIGH,
.gpio13 = GPIO_LEVEL_HIGH,
.gpio14 = GPIO_LEVEL_HIGH,
.gpio16 = GPIO_LEVEL_HIGH,
.gpio17 = GPIO_LEVEL_HIGH,
.gpio18 = GPIO_LEVEL_HIGH,
.gpio25 = GPIO_LEVEL_HIGH,
.gpio27 = GPIO_LEVEL_HIGH,
.gpio29 = GPIO_LEVEL_HIGH,
.gpio30 = GPIO_LEVEL_HIGH,
.gpio31 = GPIO_LEVEL_HIGH,
};
static const struct pch_gpio_set1 pch_gpio_set1_reset = {
.gpio24 = GPIO_RESET_RSMRST,
};
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
.gpio13 = GPIO_INVERT,
};
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
.gpio18 = GPIO_BLINK,
};
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio32 = GPIO_MODE_GPIO,
.gpio33 = GPIO_MODE_GPIO,
.gpio34 = GPIO_MODE_GPIO,
.gpio35 = GPIO_MODE_GPIO,
.gpio36 = GPIO_MODE_GPIO,
.gpio37 = GPIO_MODE_GPIO,
.gpio38 = GPIO_MODE_GPIO,
.gpio39 = GPIO_MODE_GPIO,
.gpio48 = GPIO_MODE_GPIO,
.gpio49 = GPIO_MODE_GPIO,
.gpio57 = GPIO_MODE_GPIO,
};
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
.gpio34 = GPIO_DIR_INPUT,
.gpio36 = GPIO_DIR_INPUT,
.gpio37 = GPIO_DIR_INPUT,
.gpio38 = GPIO_DIR_INPUT,
.gpio39 = GPIO_DIR_INPUT,
.gpio40 = GPIO_DIR_INPUT,
.gpio41 = GPIO_DIR_INPUT,
.gpio42 = GPIO_DIR_INPUT,
.gpio43 = GPIO_DIR_INPUT,
.gpio44 = GPIO_DIR_INPUT,
.gpio45 = GPIO_DIR_INPUT,
.gpio46 = GPIO_DIR_INPUT,
.gpio47 = GPIO_DIR_INPUT,
.gpio48 = GPIO_DIR_INPUT,
.gpio49 = GPIO_DIR_INPUT,
.gpio50 = GPIO_DIR_INPUT,
.gpio52 = GPIO_DIR_INPUT,
.gpio54 = GPIO_DIR_INPUT,
.gpio56 = GPIO_DIR_INPUT,
.gpio57 = GPIO_DIR_INPUT,
.gpio58 = GPIO_DIR_INPUT,
.gpio59 = GPIO_DIR_INPUT,
.gpio60 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio38 = GPIO_LEVEL_HIGH,
.gpio39 = GPIO_LEVEL_HIGH,
.gpio40 = GPIO_LEVEL_HIGH,
.gpio41 = GPIO_LEVEL_HIGH,
.gpio42 = GPIO_LEVEL_HIGH,
.gpio43 = GPIO_LEVEL_HIGH,
.gpio44 = GPIO_LEVEL_HIGH,
.gpio45 = GPIO_LEVEL_HIGH,
.gpio46 = GPIO_LEVEL_HIGH,
.gpio48 = GPIO_LEVEL_HIGH,
.gpio50 = GPIO_LEVEL_HIGH,
.gpio52 = GPIO_LEVEL_HIGH,
.gpio54 = GPIO_LEVEL_HIGH,
.gpio57 = GPIO_LEVEL_HIGH,
.gpio58 = GPIO_LEVEL_HIGH,
.gpio59 = GPIO_LEVEL_HIGH,
.gpio60 = GPIO_LEVEL_HIGH,
.gpio62 = GPIO_LEVEL_HIGH,
};
static const struct pch_gpio_set2 pch_gpio_set2_reset = {
};
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
.gpio68 = GPIO_MODE_GPIO,
.gpio69 = GPIO_MODE_GPIO,
.gpio72 = GPIO_MODE_GPIO,
};
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
.gpio68 = GPIO_DIR_INPUT,
.gpio69 = GPIO_DIR_INPUT,
.gpio70 = GPIO_DIR_INPUT,
.gpio71 = GPIO_DIR_INPUT,
.gpio72 = GPIO_DIR_INPUT,
.gpio73 = GPIO_DIR_INPUT,
.gpio74 = GPIO_DIR_INPUT,
.gpio75 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set3 pch_gpio_set3_level = {
.gpio64 = GPIO_LEVEL_HIGH,
.gpio65 = GPIO_LEVEL_HIGH,
.gpio66 = GPIO_LEVEL_HIGH,
.gpio67 = GPIO_LEVEL_HIGH,
.gpio68 = GPIO_LEVEL_HIGH,
.gpio72 = GPIO_LEVEL_HIGH,
.gpio74 = GPIO_LEVEL_HIGH,
.gpio75 = GPIO_LEVEL_HIGH,
};
static const struct pch_gpio_set3 pch_gpio_set3_reset = {
};
const struct pch_gpio_map mainboard_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
.level = &pch_gpio_set1_level,
.blink = &pch_gpio_set1_blink,
.invert = &pch_gpio_set1_invert,
.reset = &pch_gpio_set1_reset,
},
.set2 = {
.mode = &pch_gpio_set2_mode,
.direction = &pch_gpio_set2_direction,
.level = &pch_gpio_set2_level,
.reset = &pch_gpio_set2_reset,
},
.set3 = {
.mode = &pch_gpio_set3_mode,
.direction = &pch_gpio_set3_direction,
.level = &pch_gpio_set3_level,
.reset = &pch_gpio_set3_reset,
},
};

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src/mainboard/gigabyte/ga-h77m-d3h/hda_verb.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
0x11060441, /* Codec Vendor / Device ID: VIA VT2020 */
0x1458a014, /* Subsystem ID */
13, /* Number of 4 dword sets */
AZALIA_SUBVENDOR(2, 0x1458a014),
AZALIA_PIN_CFG(2, 0x24, 0x01014010),
AZALIA_PIN_CFG(2, 0x25, 0x410110f0),
AZALIA_PIN_CFG(2, 0x26, 0x410160f0),
AZALIA_PIN_CFG(2, 0x27, 0x410120f0),
AZALIA_PIN_CFG(2, 0x28, 0x0221401f),
AZALIA_PIN_CFG(2, 0x29, 0x02a19037),
AZALIA_PIN_CFG(2, 0x2a, 0x0181303e),
AZALIA_PIN_CFG(2, 0x2b, 0x01a19036),
AZALIA_PIN_CFG(2, 0x2c, 0x503701f0),
AZALIA_PIN_CFG(2, 0x2d, 0x474511f0),
AZALIA_PIN_CFG(2, 0x2e, 0x074521f0),
AZALIA_PIN_CFG(2, 0x2f, 0x47c521f0),
0x80862806, /* Codec Vendor / Device ID: Intel */
0x80860101, /* Subsystem ID */
4, /* Number of 4 dword sets */
AZALIA_SUBVENDOR(3, 0x80860101),
AZALIA_PIN_CFG(3, 0x05, 0x58560010),
AZALIA_PIN_CFG(3, 0x06, 0x58560020),
AZALIA_PIN_CFG(3, 0x07, 0x18560030),
};
const u32 pc_beep_verbs[0] = {};
AZALIA_ARRAY_SIZES;

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src/mainboard/gigabyte/ga-h77m-d3h/thermal.h Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef GAB75MD3H_THERMAL_H
#define GAB75MD3H_THERMAL_H
/* Temperature which OS will shutdown at */
#define CRITICAL_TEMPERATURE 100
/* Temperature which OS will throttle CPU */
#define PASSIVE_TEMPERATURE 90
#endif